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....is analyzed, using a range of applications. 1 Introduction The biggest obstacle to the more widespread use of reconfigurable computing systems lies in the difficulty of developing application programs for them. FPGAs are typically programmed using hardware description languages such as VHDL [23]. Application programmers are typically not trained in these hardware description languages and usually prefer a higher level, algorithmic programming language to express their applications. Turning a computation into a circuit, rather than into a sequence of CPU instructions, may seem to offer ....

D. Perry. VHDL. McGraw-Hill, 1993.

....must be created for each basic gate in the library. The behavioral view describes the logic function and the timing characteristic of the gate. An acceptable way of creating a behavioral view, adapted from semiconductor circuit design, is the use of an HDL, such as Verilog HDL [5] 18] and VHDL [19], 6] The Rochester design environment supports the use of both of these languages for behavioral modeling and simulation of RSFQ circuits [3] 11] The initial version of a behavioral view is created directly from the cell specification (e.g. a Mealy diagram) and does not require any ....

D. Perry, VHDL, McGraw-Hill, 1991.

....As we are seeking a close translation of the digital equalizer model, all the modules should be mapped to their VHDL counterparts as precisely as possible. First of all, what we encounter is the data type conversion. After examining the data types used in Haskell [1] and VHDL [17] [18], we may get a good mapping of the data types. Table 2.1 shows a mapping of the basic data types used in the equalizer model. TYPE Haskell VHDL Numeric Integer Integer Float Double Real Complex Record Logic Bool Bool Timed TVal Enumerated TVal A Record Compound Vector Array Tuple(x,y) ....

....one of VHDL s three object types, namely signal, variable and constant. It is characterized as a physical wire. Signal objects are used to connect entities together to form models. Signals are the means for communication of dynamic data between entities. A signal declaration in VHDL is as follows [18]: Signal signal name : s i gna l type [ i n i t i a l va l ue ] The keyword Signal is followed by one or more signal names. Each signal name will create a new signal. The signal type speci es the data type of the information that the signal will contain. Finally the signal can contain an ....

Douglas L. Perry VHDL, Chapter 4. McGraw-Hill, Inc., 1991.

....(HDLs) All EA components, like the population (including the initialization) the selection mechanism and the fitness evaluation, are directly implemented as hardware modules that can be synthesized on a target technology. This can be an ASIC or an FPGA. For our implementation we used VHDL [7,8], since it is widely used and a large set of commercial tools exist. The VHDL code describes the different components in a structured way that allows for an easy reuse. This becomes the key of today s successful hardware projects, since without a concise reuse methodology the complexity cannot be ....

....supports different description methods, i.e. structural, behaviour and data flow. Signal delays can be modelled. Availability of complex data types, like integer, real, or array. Structured algorithms can be described by procedures and functions. For more details on VHDL see e.g. [7,8]. 3. EA Implementation in VHDL For all EA components described in Section 2.1, a VHDL module has been developed. First, the overall structure is outlined. Due to page limitation, a complete description of all modules cannot be given. Instead, we briefly discuss the main features of each element ....

D. Perry, VHDL, McGraw Hill, 1998

....is the basis of the realization of the system. Usually, a kind of process algebra formalism We speak of implementation although we actually might deal with an abstraction of a real like CCS [Mil89] ACP [BV94] LOTOS [BB89] or another (semi )formal design notion like B(PN) BH93] VHDL [Per91] or UML [SP99] is employed. This step is shown in the lower left corner of Figure 1.1. The verification of the implemented system is a further step. Its aim is to guarantee the correctness of the functionality. In practice, verification is often more important for debugging the design instead ....

D. Perry. VHDL. McGraw-Hill, New York, 1991.

.... effectiveness of the proposed assignment technique, we have syn thesized the following conditional intensive VHDL descriptions: the dealer process of Blackjack [15] Fancy [19] the controller for the AutoPilot of an Unmanned Aerial Vehicle (UAV) 21] a subcircuit of a Vending machine controller [28], and the graphics controller [29] Table 3 shows the synthesis results. Each description is scheduled to satisfy the resource constraints specified in column Resources. Assignment 1 is a feasible assignment which satisfies the resource constraints, but does not focus on minimizing clock period. ....

D. Perry. VHDL. McGraw-Hill, New York, NY 10020, 1989.

....the behavior of components of a circuit design at a high level. Simulation is performed based on these high level components. The high level functions indicate transformations on data as the data move from one storage device to another. This type of simulation has been used in VHDL simulation [80] and system level simulation. ffl Gate level logic simulation : Gate level simulation is relatively faster and nearly as accurate as switch level simulation. A small set of primitive components, such as NOT, AND, OR, NAND, and NOR gates are supported. The propagation delay of gates can be ....

Douglas L. Perry, "VHDL," McGraw-Hill, 1994.

....performance e ects of these optimizations on a four loop sequence are shown. 1 Introduction Perhaps the biggest obstacle to the widespread use of recon gurable computing systems lies in the diculty of programming them. FPGAs are typically programmed in hardware description languages such as VHDL [12]. These languages require great # #### #### ## ######### ####### ##### ## ### ##### ######## ########## ######## ################# attention to detail, including issues such as timing and low level synchronization. The Cameron Project [7, 10] has created a highlevel algorithmic language, named ....

D. Perry. ####. McGraw-Hill, 1993.

....image compression [22] and neural networks [14] Unfortunately, the biggest obstacle to the more widespread use of recon gurable computing systems lies in the dicultyofdeveloping application programs. FPGAs are typically programmed using behavioral hardware description languages such as VHDL [31] and Verilog. These languages require great attention to detail suchastiming issues and low level synchronization. However, application programmers are typically not trained in these hardware description languages and may be reluctant to learn them. They usually prefer a higher level, algorithmic ....

D. Perry. ####. McGraw-Hill, 1993.

....in VHDL In this section, we discuss the basic modeling strategy for specification level and functional level models in VHDL. VHDL was selected as our modeling language because it allows simulation over many different levels of abstraction and is widely accepted as a standard for modeling hardware [5, 7, 8]. In all our models, we follow the VHDL modeling conventions listed below. 1. High level behaviors are modeled as processes or sets of communicating processes. 2. All the registers or buffers are modeled as variables within processes. 3. Processes communicate with each other using global ....

....t=276.0; q=0.0; for (k=1; k =400; k ) x[k] q y[k]3(r3z[k 10] t3z[k 11] g Figure 23: Livermore Loop 1: Hydro excerpt. main( f register int lw; register int j, l; double x[1002] y[1002] for (l=7; l =107; l 50) f lw=l; for (j=30; j =870; j =5) x[j 1]0 =x[lw ]3y[j] x[l 1] y[5]3x[l 1] g g Figure 24: Livermore Loop 4: Banded linear equations. translation from C to the RP instruction set has been carried out manually. Although the three loops do not test the instruction set of the RP exhaustively, they incorporate a large number of the RP features. For example, VARs ....

D. L. Perry, VHDL, McGraw-Hill, Inc., 1991.

....successfully employed the Compass RTL synthesizer on the Synopsys targeted VHDL. The applicability of tools like EXV to asynchronous design is far from obvious. EXV is inherently a tool for designing synchronous logic. It generates RTL VHDL that is commonly synthesized according to the model [14] where clouds of combinational logic are interconnected through synchronous registers. EXV employs a unit delay model, and simulates the design by advancing a clock. To bypass these difficulties, we have defined a design and simulation discipline, as described in Sections 4 and 6. We also ....

....target synthesis tool, and the target synchronous design styles (one hot vs. encoded states, two valued vs. multivalued logic, single vs. two phased clocks) The resulting VHDL code is synthesized, by tools like Synopsys, into a netlist according to the common architecture of register and cloud [14] (Fig. 11) We would like to take advantage of the general structure and of the combinational logic clouds, but we need to get rid of the clocked registers, thus converting a synchronous circuit into an asynchronous one. Many methods can be conceived for the conversion. We prefer methods which ....

D.L. Perry, VHDL, 2nd ed., McGraw-Hill, 1994, Ch. 9,10: Synthesis.

....L =2 13.04 19.52 36.03 39.08 (met) met) met) Total cell area L =1 7.16 7.09 7.05 7. 34 10 5 [m 2 ] L =2 17.88 17.82 17.79 18.68 Net switching L =1 243.7 130.3 69.6 35.0 p ower [mW] L =2 611.3 329.4 182.1 87.3 eled the proposedarc hitecW#5 by VHDL as an edgetriggeredsync hronous system [10]. Table 3 sho s the estimation of the synthesis results, here the Synopsis design tools Ver.1998.02 [11] are used ith the linear model of the standardcan library EXDLIB provided by VDEC for 0.5 m triple metal CMOStec hnology [12] The environments are set as follo s: No drivingciv is set to ....

D.L. Perry, VHDL, McGraw-Hill, Inc., 1994.

....to the STG presented in Figure 2. A. Behavioral VHDL. From the STG VHDL code can be generated which represents the behavior of the STG. The main characteristic of an STG ( or Petri net) is that each place can be considered a state. This corresponds to a machine with more than one active state [7]. rejsend down: BLOCK ( places(8) 1 AND places(9) 1 ) BEGIN rejsend int = GUARDED 0 ; places(8) GUARDED 0 ; places(9) GUARDED 0 ; places(10) GUARDED 1 ; END block rejsend down; The dynamic behavior of the places is represented by a vector of booleans. If a token ....

Douglas E. Perry. VHDL. McGraw-Hill, 1991.

....or reactive systems in several application fields. However, these formalisms deal with asynchronous systems mostly. A distinct class of computational systems is that of synchronous systems. It includes programming languages such as Esterel [2] hardware description languages such as VHDL [22], and specification formalisms such as evolving algebras [12, 13, 14] Works on the verification of such systems either explore restricted techniques such as finite model checkers, or depend on idiosyncrasies of a particular notation, or are not mature yet. This paper introduces a formalism named ....

D. L. Perry. VHDL. McGraw-Hill, 1991.

....or reactive systems in several application fields. However, these formalisms deal with asynchronous systems mostly. A distinct class of computational systems is that of synchronous systems. It includes programming languages such as Esterel [2] hardware description languages such as VHDL [21], and specification formalisms such as evolving algebras [12, 13] Works on the verification of such systems either explore restricted techniques such as finite modelcheckers, or depend on idiosyncrasies of a particular notation, or are not mature yet. This paper introduces a formalism named ....

D. L. Perry. VHDL. McGraw-Hill, 1991.

....a need was felt to standardize HDLs so that a company could select one standard HDL for use and turn to CAD tool vendors for its support. The past decade has seen an explosion of HDLs emerging in the market; a few of them being CONLAN [43] and ELLA [13, 34] in Europe, and Verilog [48] and VHDL [29, 39, 42] in the US. Amongst these, the hardware description language VHDL has enjoyed widespread acceptance as a standard primarily due to the efforts of the United States Department of Defense (DoD) VHDL supports a hierarchical description of digital systems and can be used to describe arbitrarily large ....

....there exists a need to develop a formal, well defined, well understood, and complete specification of the semantics for the language. Furthermore, formal verification techniques using VHDL can be based only on a formal mathematical 1 It turns out that it refers to both. 2 For example, Perry [42] defines the semantics of the VHDL exit statement incorrectly. representation of its semantics. The application of formal methods towards the definition of the semantics of VHDL has been pursued since the late 1980s. Most of the investigations into formal definitions concentrate on defining the ....

Perry, D. L. VHDL, 2nd ed. McGraw--Hill, New York, NY, 1994.

....to follow the later chapters. It is intended to help a novice at VHDL to get an introduction to the language syntax and the simulation semantics. This is not a tutorial for VHDL. For a tutorial on VHDL constructs and concepts, I recommend the following books: Dr. Ashenden [1] D. L. Perry [27], Z. Nawabi [22] For a complete reference on VHDL and the semantics of simulation, refer the VHDL Language Reference Manual [11, 12] Chapter 3 Components of the VHDL Analyzer Simulator A compiler can be broadly divided into three functional units, the front end analyzer responsible for ....

Perry, D. L. VHDL, 2nd ed. McGraw--Hill, New York, NY, 1994.

.... [13, 47, 3, 23] However, these 30 studies also show that, even within the same application domain, some executions perform better under aggressive cancellation [2, 41] In studies involving the simulation of digital systems [39] described using the hardware description language VHDL [29, 37], we have observed (confirmed) that: 1. Neither cancellation strategy is clearly superior. 2. The optimal cancellation strategy is sensitive to the partitioning scheme employed for distributing the LPs on processors. 3. Different LPs within the same application operate best under different ....

....6. 2 Benchmarks used in this investigation The performance of Dynamic Cancellation relative to lazy and aggressive cancellation was compared using models from two application domains namely queuing model simulations and the simulation of digital systems using the hardware description language VHDL [37]. The results presented in this thesis have been obtained from two different Time Warp simulators one of which is a purely VHDL digital system simulator, called VAST (Appendix B) while the other is a generic Time Warp simulator called warped (Appendix A) 26] The warped project includes ....

Perry, D. L. VHDL. McGraw--Hill, New York, NY, 1991.

....parallel, with all components executing concurrently. HDLs have features to support modeling these physical phenomenon. HDLs provide ways to model basic hardware components such as wires, pins, and boolean logic. Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) [1, 20, 27] is one such hardware modeling language. It was initially developed through the US Department of Defense s VHSIC program. This development was driven by the need for a standard language for describing the structure and function of integrated circuits. It has now evolved into one of the two major ....

Perry, D. L. VHDL, 2nd ed. McGraw--Hill, New York, NY, 1994.

....with the adoption of VHDL version 7.2 as the baseline language. The current standard for the language is IEEE Std 1076 1993 and is specified in the Language Reference Manual [25] In addition to the Language Reference Manual (LRM) several reader friendly books describing VHDL are available [3, 4, 41]. VHDL is currently used in the design, development, verification, synthesis, and testing of hardware designs. The primary abstraction of a hardware description in VHDL is a design entity. It represents a hardware design that has a well defined input and output and performs a well defined ....

Perry, D. L. VHDL, 2nd ed. McGraw--Hill, New York, NY, 1994.

.... of computers at various levels of the design hierarchy (different levels of abstraction) The same chapter discusses the need for languages to express structure and behavior of a system, both of which are indeed characteristics of all major hardware description languages ever since (e.g. VHDL [Per94, IEE87] and Verilog [SST90] Presently, effective languages exist for most aspects of the design process with the exception of specifications. Although languages do exist for the latter, these languages are effective only in narrowly defined domains and are not of general use. Section 3 of this ....

....in a design description. The HDL can be used to simulate a design and resolve errors before hardware is built. The HDL can then be used to implement the design through synthesis. Finally, the HDL provides a means of documenting a design. The two main languages for hardware description are VHDL [Per94, IEE87] and Verilog [SST90] Verilog and VHDL are both formal languages for the description of hardware designs. They each have a specific context free grammar for their structure (See Table 3) ABEL is another HDL, with a more limited scope than the previous two languages. To illustrate these ....

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D. L. Perry. VHDL. McGraw-Hill, Inc., 1994.

....is used as a modeling language. VHDL is inherently flat which means layered protocol specification is not possible. VHDL requires that the entity declaration of models be at the bit level and hence, communication must necessarily be modeled at the physical level, i.e. transitions on signals [7]. But if the communication has to be removed from the component model, then the entity interface to the external world will consist of function calls. However, in VHDL an entity cannot consist of function calls. It must use the standard data types like bit, integer or std logic. The model then ....

Douglas L. Perry. VHDL. 2 nd ed., McGraw-Hill, New York, 1994.

....By placing entire subtrees on the same processor good locality can be achieved. 3 Automatic Test Knowledge Extractor The Automatic Test Knowledge Extractor (ATKET) 9] is a software package which extracts information from the description of a circuit in a hardware description language like VHDL [8]. This information helps in guiding the search process and speeding up test generation. The high level knowledge about the behavior of a system can be used to combine module tests into high quality tests for complex circuits. An important part of this package was the design and implementation of a ....

D. Perry, VHDL, New York, NY, McGraw-Hill, 1991.

....This testbench is a VHDL entity with an architecture that contains a component declaration for the design, a signal declaration for each of its external connections, and an instantiation of the design, the ports of which are connected to the signals. Using such a testbench has been proposed in [5] and gives the user the full expressive power of VHDL to assign waveforms to the external inputs and to observe and evaluate the resulting responses of the design. Our tool set supports both types of simulation: timing simulation and functional simulation. For timing simulation, the VHDL netlist ....

Z. Navabi: VHDL - Analysis and Modelling of Digital Systems, McGraw-Hill, New York, 1993.

....Automatic generation not only significantly shortens the development cycle, it also allows retargeting since modifications in the architecture can be made at the specification level and the new simulator can then be automatically generated. Although a number of hardware description languages [1, 7, 9, 13] are available, these languages are not suitable for developing cycle level simulators. These languages are capable of defining the hardware to the smallest detail and result in simulators that are orders of magnitude slower than cycle level simulators. The retargeting of simulators requires ....

D.L. Perry. VHDL. McGraw-Hill, 1991.

....per project, design tools beyond the grasp of many organizations. Therefore, a community of vendors building and marketing CAD tools employing standardized HDLs have emerged. For example, it is currently possible for a company to select a standardized HDL such as ELLA [16] Verilog [18] or VHDL [17] and then choose among several CAD vendors for design tool support. Unfortunately, despite the presence of several CAD tools for each of these design languages, the adherence of a specific vendors tools to the language standard my vary. In some cases the deviation from the language standard may be ....

....by the Advanced Research Projects Agency and monitored by the Air Force Wright Laboratory under contract number F33615 93 C 1315. libraries; and so on. In general, most language definitions include at most a formal syntax specification and an informal (prose) definition of the semantics (e.g. [16, 17, 18]) In the rare case where additional formal semantics exist, they generally address only the dynamic semantics of the language s simulation behavior (e.g. 6, 13] Thus, the builders of design tools to process HDLs are often left with only informal, incomplete, prose descriptions of important ....

Perry, D. L. VHDL, 2nd ed. McGraw--Hill, New York, NY, 1994.

....a key point of our comparison was a highly automized design process together with a state of the arts target hardware. We used the sea of gates array family TC 160 G from Toshiba in 0.8 m technology which is equivalent to Siemens SCxE6 technology. For each architecture and field order a VHDL [Per94] description on the register transfer level was provided. We used Verilog HDL from Cadence Design Systems Inc. The next, and major, design step is the synthesis which consists of two processes, translation and optimization. To these processes we applied the Synopsys 2.2b design compiler which is ....

D.L. Perry. VHDL. McGraw-Hill, New York, 2nd edition, 1994.

....Automatic generation not only significantly shortens the development cycle, it also allows retargeting since modifications in the architecture can be made at the specification level and the new simulator can then be automatically generated. Although a number of hardware description languages [1, 7, 9, 13] are available, these languages are not suitable for developing cycle level simulators. These languages are capable of defining the hardware to the smallest detail and result in simulators that are orders of magnitude slower than cycle level simulators. The retargeting of simulators requires ....

D.L. Perry. VHDL. McGraw-Hill, 1991.

....timing analysis tool FEST in C. To evaluate the effectiveness of FEST, we synthesize the following conditional intensive VHDL descriptions: the dealer process of Blackjack [19] the controller for the AutoPilot of an Unmanned Aerial Vehicle (UAV) 22] and a part of the Vender example from [24]. Table 2 shows the estimation results. Each description is scheduled to satisfy the resource constraints specified in Figure 2 for the dealer process and in Figure 5 for the UAV example. The relevant portions of the CFG for the dealer process is shown in Figure 2, and the mapping of the CFG ....

D. Perry. VHDL. McGraw-Hill, New York, NY 10020, 1989.

....get in extracting the BDD based description of a FSM directly from the VHDL code instead of from a gate level implementation. The considered circuits come from both industrial and academic environments. Those with the ctrl suffix are parts of the vending machine reported in the VHDL book of Perry [21] and the others are telecom controllers. For each circuit we present the total number of primary inputs and primary outputs; then, the number of states and the number of BDD nodes of the global relation of the FSM associated to the circuit in the case such relation is extracted from the VHDL ....

D. L. Perry, VHDL, McGraw-Hill, 1993.

....the number of outputs of the circuit limits the number of parallel scan chains that can be formed. We illustrate with the change maker circuit, whose connectivity graph is shown in Figure 6. The change maker circuit is one of the three subcircuits comprising a controller for a vending machine [21]. It should be noted that the connectivity graph of Figure 6 also includes a comparator node with a 1 bit output which can perform the = operation. The change maker circuit has inputs reset (1 bit) item stb (1 bit) total (8 bits) price (8 bits) and num coins for a total of 26 input pins. The ....

D. Perry. VHDL. McGraw-Hill, New York, NY 10020, 1989.

....and compiling applications will consist of partitioning the algorithm between a host processor and reconfigurable modules, and devising ways of producing efficient FPGA configurations for each piece of code. Presently, FPGAs are programmed in hardware description languages, such as VHDL [20]. While such languages are suitable for programming chips that are used as glue logic in digital circuits, they are poorly suited for the kind of algorithmic expression that takes place in applications programming. The Cameron project provides Khoros with a programming language for expressing ....

D. Perry. VHDL. McGraw-Hill, 1993.

....liveness and boundedness [6] VHDL is a standard hardware description language used to design digital systems, allowing the model to be clearly specified, simulated and synthesised. The specifications of the systems designed with VHDL can be hierarchically structured and properly represented [7]. The joining between VHDL and PNs is considered to be an acceptable solution. This was studied and applied with success in the specification of parallel controllers [8] An identical evaluation is being carried out on the EDgAR platform, to implement systems that are more complex than those ....

Douglas L. Perry. VHDL. McGraw-Hill, 1991.

.... scanners and parsers, and the usefulness of tools like Lex and Yacc In synchronous circuit design, it is the usual model of communicating Mealy machines (FSM) Most hardware description formalisms (e.g. Bli90,CLM91] are naturally synchronous, or contain a significant synchronous subset [Per93] As a matter of fact, the compilation and verification of synchronous programs borrow many techniques from circuit CAD. However, while hardware description languages can be directly used to describe the data part of a circuit, they are of little help in designing complex hardware controllers. ....

D. Perry. VHDL. McGraw-Hill, 1993.

.... effectiveness of the proposed assignment technique, we have synthesized the following conditional intensive VHDL descriptions: the dealer process of Blackjack [21] Fancy [40] the controller for the AutoPilot of an Unmanned Aerial Vehicle (UAV) 42] a subcircuit of a Vending machine controller [48], and the graphics controller [49] Table 3 shows the synthesis results. Each description is scheduled to satisfy the resource constraints specified in column Resources. Assignment 1 is a feasible assignment which satisfies the resource constraints, but does not focus on minimizing clock period. ....

D. Perry. VHDL. McGraw-Hill, New York, NY 10020, 1989.

....CAD tools allow designers to work at higher levels of abstraction by automating parts of the design process, while HDLs allow designers to communicate their design intent to these CAD tools. A large number of different hardware description languages have been developed in recent years. VHDL [21] and Verilog [24] have gained the widest acceptance in academia and industry. While they differ in their syntax and semantics, both represent designs using a model based on an interconnected set of components. Each component can be described by its behaviour or by a set of lower level ....

Perry, D.L., VHDL. McGraw Hill, 1991.

....decomposed into sub designs and how those sub designs are interconnected. With VHDL, the function of a design is described using familiar programming constructs. VHDL allows a design to be simulated so that several design alternatives can be compared and tested before a hardware prototype is built [2, 5]. VSPEC is an extension of VHDL. It allows designs to be specified in a declarative fashion as opposed to the operational style of VHDL. With VSPEC, the desired characteristics of a digital circuit are described instead of a single design artifact exhibiting these characteristics. VSPEC does not ....

Douglas L. Perry. VHDL. McGraw-Hill, Inc., New York, NY, 1991.

....: D c R c . The only difference is that the feasible outputs are constrained to be well defined over the legal inputs. Figure 3 shows an interface specification for a search component. The specification is written in vspec [ Baraona et al. 1995 ] an interface specification language for vhdl [ Perry, 1991 ] The port clause defines the domain and range of the component. The requires and ensures clauses represent the input and output conditions of the component respectively. The post operator is used to indicate the value of a variable after the component executes. 2.3 Evaluation Interface ....

D. Perry. VHDL. McGraw-Hill, New York, NY, 1st edition, 1991.

....case is the powerful Synopsys VHDL simulator vhdlsim [3] For timing simulation, the VHDL netlist written by the MAX plusII compiler is slightly modified and embedded in an automatically generated VHDL testbench. The user may describe his stimuli within this testbench using VHDL, as proposed in [5]. For functional simulation, a VHDL model of the design is generated directly from the original AHDL description. Design hierarchy, busses and all symbolic names of instances, machine states and signals are preserved in this model. It is embedded in the same testbench as the timing model so that ....

Z. Navabi: VHDL - Analysis and Modelling of Digital Systems, McGraw-Hill, New York, 1993.

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D. Perry. VHDL. McGraw-Hill, 1993.

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Z. Navabi: VHDL Analysis and Modeling of Digital Systems. McGraw-Hill, Inc., 1993.

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Douglas L. Perry, VHDL, McGraw-Hill, 1993

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