P. B. Gibbons. A More Practical PRAM Model. In Ist Symposium on Parallel Algorithms and Architectures, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....powerful. We further describe why it is useful to bridge these elds and then proceed to the main results in this paper. 1. 1 Asynchronous Parallel Computation Executing parallel programs on heterogeneous processors is studied intensely in the area of asynchronous parallel computation [20, 19, 34, 32, 28, 5, 3, 2]. In this eld, the goal is to run a parallel program that is written assuming synchronization barriers, on a collection of asynchronous processors that do not have a synchronization primitive. In some special cases, such as numerical algorithms, the structure of the parallel program may be ....

P. B. Gibbons. A more practical PRAM model. In Proc. of the 1st ACM Symposium on Parallel Architectures and Algorithms (SPAA), pages 158-168, June 1989.

....memory access conflict resolution schemes. The relationship between different basic PRAM models is discussed in [11] Other variations of the PRAM model have been introduced to model shared memory parallel computers that are asynchronous (APRAM model [7] and semi asynchronous (PPRAM phase PRAM [13]) Since most commercial parallel computers are a collection of processor memory pairs that operate asynchronously and communicate via an interconnection net work, efforts have been made to develop models for these computers that are more accurate than the asynchronous PRAM. Two attempts in this ....

P. Gibbons, A more practical PRAM model, Proceedings ACMSPAA, 158-168, 1989.

....amount of time as a local computation step, whereas, in a real parallel computer architecture, a communication step is far more time consuming. There are several PRAM based models that include aspects of real parallel machines, such as latency [2, 3, 21] memory contention [14, 13] and asynchrony [6, 12]. The BSP model [22] and the LogP model [7, 9] are models of parallel computation that consist of a collection of processors that communicate using message passing. These models are more realistic, because they include several aspects of real parallel computers. Both models characterise a ....

P.B. Gibbons. A more practical PRAM model. In Proceedings of the 1989.

....and realizable parallel computers is being bridged by current research. For example, memory access simulation in other architectures is the subject of a large body of literature surveyed in [98] for some recent work see [49, 87, 97] Computation on asynchronous PRAMs are the subject of [29, 31, 45, 75, 78]. The reliability of semiconductor memories has been thoroughly studied, and a survey can be found in [89] while the theory of error detecting and correcting codes is reviewed in [76] The fault tolerant issues of the interconnection networks used to integrate processors and memory modules are ....

....(as in [99] is exploited to our advantage. Asynchronous versions of the PRAM is a subject of recent research. Various means of relaxing the strict synchronization requirements of the standard PRAM have been used to show that efficient algorithms can be efficiently executed on asynchronous models [29, 31, 45, 78, 75]. A simple randomized algorithm that serves as a basis for simulating arbitrary PRAM algorithms on an asynchronous PRAM is presented by Martel et al. in [75] This randomized asynchronous simulation has very good expected performance for the Write All problem when the adversary is off line. Other ....

P. Gibbons, "A More Practical PRAM Model," in Proc. of the 1989.

....memory accesses are unit cost and that synchronization is unnecessary (because processors run in lockstep) These assumptions simplify analysis, but do not reflect real computers, particularly those with caches. For this reason, PRAM extensions model non uniform memory and processor asynchrony [3, 10, 33, 20]. The new models are more descriptive and complex than traditional PRAM models, but still do not accurately describe cache coherent parallel computers. Perhaps this paper will help inspire PRAM extensions that describe this important type of computers. Culler et al. described another model of ....

Phillip B. Gibbons. A More Practical PRAM Model. In Proceedings of the First ACM Symposium on Parallel Algorithms and Architectures (SPAA), pages 158 168, June 1989.

....is a convenient model for which numerous ecient algorithms have been developed [9, 11, 20] However, pram makes assumptions that, given the current state of technology, make it dicult for it to be implemented as a scalable architecture. A number of works address and deal with this problem (e.g. [6, 7, 12, 17, 26, 25, 28, 29, 32]) Some approaches preserve pram as a model for algorithm designers and provide algorithmic simulations of pram algorithms on other platforms. It has been shown that solutions for a particular problem can be used as building blocks in constructing such simulations (e.g. 8, 21, 26, 30] This ....

....last column shows the ratio of the number to (p 1) Observe that the number of such permutations has to be at least p 1 (cf. Theorem 3. 3) For the largest prime that we can evaluate given modest computing resources, p = 13, we plot the histogram (see Figure 3) of the fraction of permutations on [12] that yield a given number of left to right maxima. p (p 1) L(p) equal to L(p) ratio 2 1 1 1 1 3 2 3 2 1 5 24 9 8 0.33 7 720 17 12 0.016 11 3628800 37 60 0.000016 13 479001600 49 48 0.0000001 17 20922789888000 75 Still running Unknown Table 1: Summary of exhaustive search. In the ....

Gibbons, P.: A More Practical PRAM Model. Proc. of the

....term, because of timing uncertainties introduced by variations in instruction complexity, page faults, cache misses, and operating system activities such as preemption or swapping. A number of researchers have noted this mismatch, and have proposed the asynchronous PRAM model as an alternative [16, 17, 21, 41]. In this model, asynchronous processes communicate by applying atomic read and write operations to the shared memory 2 . Techniques for implementing these memory locations, often called atomic registers, have also received considerable attention [13, 14, 32, 35, 40, 43, 44] Much of the work ....

....objects, implying that despite the weakness of the model, certain problems do have wait free solutions. Perhaps the most general contribution is to raise basic questions about the value of the asynchronous PRAM model. Although some synchronous PRAM algorithms can be adapted to asynchronous PRAM [16, 17, 21, 41], our results show that there is little hope of constructing useful highly concurrent long lived data structures in this model. Fortunately, however, one can argue that asynchronous PRAM is an incomplete re ection of current practice. Starting with the IBM System 370 architecture [30] in the ....

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P.B. Gibbons. A more practical PRAM model. In Proceedings of the Symposium on Parallel Algorithms and Architectures, pages 158-168, Santa Fe, NM, June 1989.

....These simplifying assumptions about the underlying communication metric are not unrealistic for the iPSC systems. The performance measurements in [19] prove that (1) and (3) are true for these systems. 2) and (4) are assumptions generally agreed upon by researchers of parallel systems[3, 11,13]. The last assumption should be modified for more detailed applications of the cost metric. However, it is a very reasonable assumption for the iPSC system, especially when messages are small. The performance measurement work [19] shows that the greatest communication cost is in the start up ....

Gibbons, P., "A More Practical PRAM Model", International Computer Science Institute, Berkeley, CA. Technical Report TR-89-019, 1989.

....problematic for the PCS model where processing units (machines or processes) may be arbitrarily snatched or get started by the external system. We propose a novel asynchronous complexity criterion which is simpler and more adequate for the PCS model than the previously suggested criteria ([15, 14, 6, 1, 2]) With our criterion, the adversary is not restricted and can choose the worst execution order. Consequently, any PCS algorithm must be nonblocking. Thus we must allow the use of non blocking synchronization primitives such as Fetch and Add [5] or Test and set in the PCS model. The proposed ....

....time of general asynchronous PRAM algorithms is applicable to PCS algorithms. Therefore, we rst focus on the asynchronous PRAM model. Several suggestions have been made as to how to analyze asynchronous execution, particularly for the PRAM model which is the relevant model for this work. Gibbons [6] introduces a model in which the computation is divided into phases which are separated by barrier synchronizations. The length of a phase is the length of the longest computation in it. The APRAM of Cole and Zajicek [1] does not require any synchronization, but the algorithm is restricted to ....

P. B. Gibbons. A more practical PRAM model. In Symp. Parallel Algorithms & Architectures, pages 158-168, Jun 1989.

....The PRAM model assumesconflict free accessesto shared memory (assigning unit cost for memory accesses) and zero cost for synchronization. The PRAM model has been augmented with additional parameters to account for memory access latency [4] memory access conflicts [5] and cost of synchronization [15, 9]. The Bulk Synchronous Parallel (BSP) model [28] and the LogP model [11] are departures from the PRAM models, and attempt to realistically bridge the gap between theory and practice. Similarly, considerable effort has been expended in the area of performance evaluation in developing simple ....

P. B. Gibbons. A More Practical PRAM Model. In Proceedings of the First Annual ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, 1989.

....and those of scheduling theory. We further describe these elds and then proceed to describe the main results in this paper. 1. 1 Asynchronous Parallel Computation Executing parallel programs on heterogeneous processors is studied intensely in the area of asynchronous parallel computation [16, 15, 29, 28, 24, 5, 3, 2]. In this eld, the goal is to run a parallel program written assuming synchronization barriers, on a collection of asynchronous processors that do not have a synchronization primitive. Processors are assumed to be arbitrarily erratic. That is, a processor may initially run so slowly that it is ....

P. B. Gibbons. A more practical PRAM model. In Proc. of the 1st ACM Symposium on Parallel Architectures and Algorithms, pages 158-168, June 1989.

....since it assumes that all processors work synchronously and that interprocessor communication is free. Different variations to the basic PRAM model have been proposed to overcome these limitations in an attempt to obtain a more practical model while preserving great part of its simplicity [1, 2, 7, 9]. Another approach which is being seriously considered as the basis of a general purpose parallel computation is the BSP model (Bulk Synchronous Parallel) It was proposed by Leslie G. Valiant in 1990 [17] as a bridge between theory and practice. The BSP model views a parallel machine as a set of ....

P. B. Gibbons. A More Practical PRAM Model. In Proceedings of the ACM Symposium on Parallel Algorithms anA . rchitectures, pages 158--168, 1989.

....measures. This problem has spurred the development of several extensions of the PRAM which attempt to make the model more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [Gib89] and APRAM [CZ89] communication costs such as network latency and bandwidth (e.g. the LPRAM [ACS90] Postal Model [BNK92] BSP [Val90] and LogP [CKP 93] and memory hierarchy, reflecting the effects of multileveled memory such as differing access times for registers, local cache, main ....

....the addition of more resource metrics to the PRAM model in order to gain improved performance measures. 4.1 Asynchronous models Among the first extensions to the PRAM were the Phase PRAM and APRAM models, which incorporate some notion of asynchronous execution. 4.1. 1 Phase PRAM The Phase PRAM [Gib89] extends the PRAM model with semi asynchrony. A Phase PRAM machine consists of a shared global memory, a set of P sequential processors, and a private local memory for each processor. The computational task is separated into a set of phases of asynchronous execution, each ended by an explicit ....

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P. B. Gibbons, "A more practical PRAM model," in Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pp. 158--168, ACM, 1989.

....algorithms. This problem has spurred the development of several extensions of the PRAM which attempt to make the model more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [33] and APRAM [18] communication costs such as network latency and bandwidth (e.g. the LPRAM [4] the Postal Model [9] BSP [82] LogP [25] and memory hierarchy such as the models discussed in the previous paragraph. In practice, both the performance of inter connection networks which connect ....

....This problem has spurred the development of several extensions of the PRAM which attempt to make the model 17 18 more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [33] and APRAM [18] communication costs such as network latency and bandwidth (e.g. the LPRAM [4] Postal Model [9] BSP [82] and LogP [25] and memory hierarchy, reflecting the effects of multileveled memory such as differing access times for registers, local cache, main memory, and disk I O ....

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P.B. Gibbons. A more practical PRAM model. In Proc. of the Symposium on Parallel Arch. and Algorithms, pages 158--168, Santa Fe, New Mexico, June 1989.

....This problem has spurred the development of several extensions of the PRAM which attempt to make the model more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [Gib89] and APRAM [CZ89] communication costs such as network latency and bandwidth (e.g. the LPRAM [ACS89] Postal Model [BNK92] BSP [Val90] and LogP [CKP 93] and memory hierarchy, reflecting the effects of multileveled memory such as differing access times for registers, local cache, main ....

....be viewed as adding more resource metrics to the PRAM model in order to gain improved performance measures. 4.1. Asynchronous models Among the first extensions to the PRAM were the Phase PRAM and APRAM models, which incorporate some notion of asynchronous execution. Phase PRAM. The Phase PRAM [Gib89] extends the PRAM model with semi asynchrony. A Phase PRAM machine consists of a shared global memory, a set of P sequential processors, and a private local memory for each processor. The computational task is separated into a set of phases of asynchronous execution, each ended by an explicit ....

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P. B. Gibbons, "A more practical PRAM model," in Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pp. 158--168, ACM, 1989.

....Bulk Synchronous Parallel (cBSP) runtime library incorporating these ideas. 1 Introduction In parallel computing, the gap separating theory and practice is wider than in sequential computing. Most theoretical models of parallel computing were designed to study algorithmic complexity [FW78, Gib89, KLadH92] and, like the physics students frictionless plane, do not reflect the state of real world technology. While useful for theoretical exploration, these models of parallel computing do not incorporate the limitations and features of existing parallel machines. Real parallel programming ....

P B Gibbons. A More Practical PRAM Model. In Proceedings of the ACM Symposium on Parallel Algorithms and Architectures, pages 158--168. Association for Computing Machinery, 1989.

....C H I N E C O MM U N I C A T I O N N E T W O R K Target Machine Network Simulation Module Event Scheduler Message Delay Model Communication Figure 3: Architectural simulation in Maya 3. 1 Modeling Parallel Architectures Several models exist for parallel architectures and computations [FW78, Gib89, Val90, CKP 93] The traditional PRAM models [FW78, Gib89] are not accurate enough for useful modeling since many important architectural aspects such as communication overheads are missing. The bulksynchronous parallel computer model [Val90] views a computation as a sequence of supersteps. ....

....Network Simulation Module Event Scheduler Message Delay Model Communication Figure 3: Architectural simulation in Maya 3. 1 Modeling Parallel Architectures Several models exist for parallel architectures and computations [FW78, Gib89, Val90, CKP 93] The traditional PRAM models [FW78, Gib89] are not accurate enough for useful modeling since many important architectural aspects such as communication overheads are missing. The bulksynchronous parallel computer model [Val90] views a computation as a sequence of supersteps. In each superstep, each component of the system is allocated a ....

P.B. Gibbons. A more practical PRAM model. In Proceedings of the 1st Annual ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, 1989.

....but its idealization has limited its value for implementing programs on real parallel systems. Hence a number of more practical models have been suggested. For instance, the Block PRAM [Aggarwal 1989] includes a 2 level memory hierarchy accounting for network latency in global memory requests. Gibbons [Gibbons 1989] discusses a family of asynchronous PRAMs with costed barrier synchronization operations to maintain memory coherency. One member of this family, the Phase LPRAM, also costs latency for global memory accesses and enables such requests to be pipelined. Valiant defines an XPRAM model [Valiant 1990a] ....

P. B. Gibbons. A More Practical PRAM Model. In SPAA'89 Proceedings of the 1989 Symposium on Parallel Algorithms and Architectures, 1989.

....that explicit use of synchronization primitives may complicate the debugging. The major disadvantage is its poor scalability. The shared memory paradigm can be implemented with either the fork join paradigm [53] PRAM [30] an idealised shared memory model, or variations of PRAM such as APRAM [34] and BSP [77] The fork join model uses forks and joins to create and reunite processes, and uses locks and barriers to co ordinate them. Processes or tasks in PRAM have local memory locations and can communication via a global common memory with constant memory latency. 2.3 Memory Consistency ....

P.B. Gibbons. A more practical pram model. In 1st Symposium on Parallel Algorithms and Architectures, 1989.

....and analysis. These models try to hide hardware details from the programmer, providing a simplified view of the machine. The utility of such models towards developing efficient algorithms for actual machines, depends on the closeness of the model to the actual machine. Several machine models [2, 3, 27, 14, 59, 17] have been proposed over the years to bridge the gap between the theoretical abstractions and the hardware. But, a complex model that incorporates all the hardware details would no longer limit the degrees of freedom to a tractable level, precluding its ease of use for algorithm development and ....

....memory and a transfer rate to access subsequent words. Mehlhorn et al. 3] use a model called the Module Parallel Computer (MPC) which incorporates contention for simultaneous accesses by different processors to the same memory module. The implicit synchronization assumption in PRAMs is removed in [27] and [14] In their models, the processors execute asynchronously, with explicit synchronization steps to enforce synchrony when needed. Valiant [59] introduces the Bulk Synchronous Parallel (BSP) model which has: a number of components, each performing processing and or memory functions; a router ....

P. B. Gibbons. A More Practical PRAM Model. In Proceedings of the First Annual ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, 1989.

....to be able to develop cost effective parallel computers in the future. Several suggestions have been made to fill the gap between the theoretical algorithms and the existing parallel computers. Some examples of the proposed models are BSP [9] LogP [3] Y PRAM [8] APRAM [2] and Phase PRAM [4]. Each of these models provides a set of restrictions and other features which should make the model more realistic. Some of the models are, however, still rather theoretical, and do not necessarily provide good enough connection between the parallel programming and parallel computers. In this ....

Gibbons P. B.: A More Practical PRAM Model. In Proceedings of 1st ACM Symposium on Parallel Algorithms and Architectures, pages 158-168, 1989.

....into the same direction: Papadimitriou and Yannakakis formulate a communication delay model and discuss the issue of using redundant local computation to avoid large communication cost [36] Aggarwal et.al. combine communication latency with the PRAM model [2] Gibbons suggests a phase PRAM model [23]. The LogP model introduced by Culler, et.al. and the C 3 model by Hambrusch and Khokhar [28] use the BSP model as a starting point, focus on the technological trend from fine grained parallel computers toward coarse grained parallel computers, and advocate portable parallel algorithm designs ....

P. Gibbons. A More Practical PRAM Model. Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, pages 158-168, 1989.

....following approach: the algorithm must work correctly for all possible interleavings of the instructions, but when analyzing the performance of the algorithms, it is assumed that there are no delays between the steps: each individual processor behaves synchronously. This approach was introduced in [Gib89] and has since been used in the analysis of other models, for example the LogP model [CKP 93] We take the same approach here. Thus, to analyze performance, we assume that at every time step, every processor performs one operation. Memory accesses are queued according 2.2 2.4 2.6 2.8 2.7 2.3 1.2 ....

P. Gibbons. A more practical PRAM model. In Proc. 1st ACM Symposium on Parallel Algorithms and Architectures, pp. 158 - 168, 1989.

....Suitable parameterization allows for straightforward estimates of run times; such estimations are the more accurate, the more the particular parallel hardware fits the model used. In our case, the programming model is the Asynchronous PRAM introduced in the parallel theory community in 1989 [13, 9, 10]. An Asynchronous PRAM (see Fig. 1) is a MIMD parallel computer with a sequentially consistent shared memory. Each processor runs with its own clock. No assumptions are made on uniformity of shared memory access times. Thus, much more than for a true PRAM, the programmer must explicitly take care ....

P. B. Gibbons. A More Practical PRAM model. In Proc. 1st Annual ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, 1989.

....not truly general purpose. Dept. of Computer Sciences, University of Texas at Austin, Austin, TX 78712. email: vlr cs.utexas.edu. This work was supported in part by NSF grant CCR GER 90 23059. Thus is not surprising that a variety of other models have been proposed in the literature, e.g. [2, 5, 6, 7, 9, 13, 15, 18, 23, 29, 32, 34, 35, 38, 40, 45, 46]) to address specific drawbacks of the pram although none of these are general purpose models. In recent years, distributed memory models that characterize the interconnection network abstractly by parameters that capture its performance have gained much attention. An early work along these lines ....

P. B. Gibbons. A more practical PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 158--168, June 1989. Full version in The Asynchronous PRAM: A semi-synchronous model for shared memory MIMD machines, PhD thesis, U.C. Berkeley 1989.

....and Shvartman [18, 19] introduce the fail stop PRAM model and describe solutions to specific algorithmic problems in this model. Kedem, Palem, and Spirakis [22] and together with Raghunathan [21] show how to execute any deterministic PRAM program on a fail stop PRAM (see also [19] Gibbons [17] and Cole and Zajicek [13] introduce the Asynchronous PRAM (A PRAM) Nishimura [25] shows how to execute specific computations using this model. Martel, Park, and Subramonian [24] provide a general execution scheme that allows any deterministic PRAM program to be executed on an A PRAM, assuming ....

P. B. Gibbons. A more practical PRAM model. In Proc. of the 1st ACM Symposium on Parallel Architectures and Algorithms, pages 158--168, June 1989.

....models confirm that the PAR model s advantages can be obtained at a reasonable cost. 1. Introduction Though the PRAM is a widely studied model of parallel computation, it is not universally accepted; several researchers have sought a replacement that overcomes some of the PRAM s drawbacks [1, 4, 5, 8, 11, 12]. The PRAM is a low level model of parallel computation. Although it is one step removed from specific hardware models, the PRAM is still a processor based model. A PRAM program must specify both processor execution and processor scheduling. The requirement to explicitly schedule processors ....

....requirement to explicitly schedule processors increases the difficulty of exposing the natural parallelism in a problem solution. The PRAM is a synchronous machine. However, many researchers argue that any massively parallel architecture must be asynchronous in order to realize maximum efficiency [4, 5, 8, 11, 12]. Research supported in part by a research grant from the Natural Sciences and Engineering Research Council y Research supported in part by a postgraduate scholarship from the Natural Sciences and Engineering Research Council Because lock step synchronization is too expensive, realistic ....

Phillip B. Gibbons, A more practical PRAM model, Proceedings of the 1st Annual ACM Symposium on Parallel Algorithms and Architectures, 1989, pp. 158--168.

....and Shvartman [16, 17] introduce the fail stop PRAM model and describe solutions to specific algorithmic problems in this model. Kedem, Palem, and Spirakis [20] and together with Raghunathan [19] show how to execute any deterministic PRAM program on a fail stop PRAM (see also [17] Gibbons [15] and Cole and Zajicek [11] introduce the A PRAM (Asynchronous PRAM) Nishimura [23] shows how to execute specific computations using this model. Martel, Subramonian, and Park [22] provide a general execution scheme that allows any deterministic PRAM program to be executed on an A PRAM, assuming a ....

P. B. Gibbons. A more practical PRAM model. In Proc. of the 1st ACM Symposium on Parallel Architectures and Algorithms, pages 158--168, June 1989.

....variants of the PRAM, each with its own particular characteristics, born out of attempts to take account of some of those factors in real machines which the pure PRAM abstracts too far away from to be realistic. Examples are: APRAM [CZ89] which incorporates asynchrony; Asynchronous PRAM [Gib89] which is asynchronous and explicitly charges for synchronisation; LPRAM [ACS90] including local memory and charges for global memory access; BPRAM [ACS89] including local memory and accounting for block transfer while charging for global memory access; etc. The HPRAM and YPRAM specifically ....

P. B. Gibbons. A more practical PRAM model. In Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, 1989. BIBLIOGRAPHY 172

....that tasks are indivisible. The two problems of routing and scheduling are often considered separately but have, at least from a theoretical point of view, remarkably similar properties and are handled in similar ways. For instance, when the model of machine incorporates barrier synchronization [39, 67], it is noticed in [67] that in a general dynamic load balancing situation there also exist phenomena that are compatible with barrier synchronization (this is not clear from a practical point of view [8, 3, 29] Similarities between the two problems may also be pointed out when load balancing ....

P.B. Gibbons. A more practical PRAM model. In Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, 1989.

....a parallel machine, and should have broad applicability with respect to existing machines. In addition, such a model should provide a platform for algorithm development and allow accurate prediction of the preformance of an algorithm. Recently, a number of models with this goal have been proposed [3, 6, 10, 13, 17, 23, 24, 25]. In most of these models, including the BSP model [24] the postal model [3] and the LogP model [6] processors are assumed to communicate using a point to point message router. Composing more involved communication operations by using the message router places a significant burden on ....

P.B. Gibbons, "A More Practical PRAM Model," Proceedings of 1989 ACM Symposium on Parallel Algorithms and Architectures, pp. 158-168, 1989.

....a parallel machine, and should have broad applicability with respect to existing machines. In addition, such a model should provide a platform for algorithm development and allow accurate prediction of the preformance of an algorithm. Recently, a number of models with this goal have been proposed [3, 5, 8, 10, 11, 15, 16, 17]. In most of these models, processors are assumed to communicate using a point to point message router. Composing more involved communication operations by having to specify fine scheduling details places a significant burden on application programmers. Furthermore, the above models do not attempt ....

P.B. Gibbons, "A More Practical PRAM Model," Proc. of 1989 ACM Symposium on Parallel Algorithms and Architectures, pp. 158-168, 1989.

....synchronous and the processors execute instructions in strict lock step. This results in inherent inefficiency due to the overhead of synchronisation on every instruction. To improve the realisability of the PRAM several practical variations of the model have been suggested by researchers. Gibbons [73] proposes the Asynchronous PRAM(APRAM) model which differs from the PRAM in that the processors run asynchronously. It uses a kind of a barrier synchronisation point amongst a set of processors and computation proceeds only if all the processors in the set have reached that logical point. Likewise ....

P. B. Gibbons. A More Practical PRAM Model. In Ist Symposium on Parallel Algorithms and Architectures, 1989.

....clobbering a more recently updated value written there, thereby producing an error. Avoiding clobbers is the main and most subtle challenge in executing a parallel program on a general asynchronous machine. The problem of asynchronous execution has been considered in several previous papers ([6, 9, 7, 18, 13, 4]) Restricting our attention to those works which deal with unrestricted asynchronous behavior [13, 4] we observe that these solutions are limited to programs of very fine granularity, i.e. PRAM programs. The salient feature of the PRAM program, central in these solutions, is that within a ....

....Previous and Related Work Dealing with asynchrony in the context of parallel shared memory systems has attracted considerable research effort in the past few years. Most of this research focuses on asynchronous variants of the PRAM. The A PRAM (Asynchronous PRAM) was introduced in [6] and [9], together with several specific algorithms. Further results on this and related models are presented in [7, 18] A general scheme for simulation of synchronous PRAMs by asynchronous PRAMs is given in [16] In these papers, however, it is either assumed that the system is equipped with explicit ....

P. B. Gibbons, "A more practical PRAM model," Proc. ACM SPAA, 158--168, 1989.

....by Lemma 5.2, the key in the root must be less than all other keys in the tree. 2 Note that Lemma 5.3 would not be true if inserted keys were sifted up from the leaves. 6 Performance In recent years, researchers have proposed many different versions of the asynchronous PRAM, or APRAM (including [9, 10, 12, 25]) most with differing notions of run time. We measure the performance of our algorithm using work, the same measure used in a series of papers on fault tolerant PRAMs [20, 19, 23] The work done by an algorithm is the total number of steps taken by all threads. In the absence of other threads, ....

P. B. Gibbons. A more practical PRAM model. In Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, Santa Fe, NM, June 1989.

....defined for such models, e.g. MPI for the message passing model, HPF for data parallel execution on distributed memory machines, BSPlib for the BSP model, or Fork95 for the PRAM model. In our case, the programming model is the Asynchronous PRAM introduced in the parallel theory community in 1989 [18, 12, 13]. An Asynchronous PRAM (see Fig. 1) is a MIMD parallel computer with a sequentially consistent shared memory. Each processor runs with its own private clock. No assumptions are made on uniformity of shared memory access times. Thus, much more than for a true PRAM, the programmer must explicitly ....

P. B. Gibbons. A More Practical PRAM model. In Proc. 1st Annual ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, 1989.

....but unfortunately, it is not well suited for predicting performance on actual parallel machines. As a consequence, a variety of alternative models have been developed,each capturing different aspects of real parallel machines, such as memory contention [MV84, KLMadH92] asynchronous execution [Gib89, CZ89] communication latency [PY88, ACS89] or communication bandwidth [ACS90] Others include network models for a variety of topologies [Lei92] sparse networks [Sny86] models which take the memory hierarchy into account [AC94] or models based on communication primitives more powerful than ....

P. B. Gibbons. A More Practical PRAM Model. In Proceedings of the ACM Symposium on Parallel Algorithms and Architectures. ACM, June 1989.

....other processors. If in a PRAM algorithm, all processors require access to different locations that happen to be within a same memory block on a practical parallel computer, then all these accesses will happen serially. Many models have been designed that remove various drawbacks of the PRAM model [1, 6, 11, 13, 9, 2, 17] But most of these models fail to promote either the bulk access locality or the data volume locality. The LogP model [4] tries to address the shortcomings of earlier models such as PRAM [13, 9] LPRAM [1] BPRAM [2] HPRAM [11] YPRAM [6] and BSP [17] A comprehensive discussion of these models ....

....Many models have been designed that remove various drawbacks of the PRAM model [1, 6, 11, 13, 9, 2, 17] But most of these models fail to promote either the bulk access locality or the data volume locality. The LogP model [4] tries to address the shortcomings of earlier models such as PRAM [13, 9], LPRAM [1] BPRAM [2] HPRAM [11] YPRAM [6] and BSP [17] A comprehensive discussion of these models and their relationship to each other is provided in [10] In the spectrum of abstract to practical parallel computers, the LogP model comes closer to practical computers compared to earlier ....

P. B. Gibbons. A more practical PRAM model. In Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, pages 158-- 168, 1989.

....The standard PRAM posits a rigid execution pattern in which all processors are synchronized by a global clock. Several variants ease this restriction. Examples which allow asynchronous execution with irregular synchronization points include the APRAM [10] and the Asynchronous PRAM [15]. Periodic synchronization between intervals of asynchronous execution is incorporated in the XPRAM [34] While these models incorporate synchronization, they do not charge an explicit cost. Although the only cost is implicit, the loss of processor utilization while waiting for other processors ....

Gibbons, P., "A More Practical PRAM Model", Proc. of the 1st Annual ACM Symposium on Parallel Algorithms and Architectures, pp. 158-168, (1989).

....cost measure appears in Section 6. 2 The QRQW Asynchronous PRAM In this section, we present the definition of the qrqw asynchronous pram model, and some observations on the algorithmic power of the model. A variety of asynchronous pram models have been studied in the literature (c.f. CZ89, Gib89, Nis90, And92, MPS92] These models account for contention in a manner most like a crcw pram, with no penalty assessed for large contention to a location. 1 An erew contention rule was not considered, 2 since most asynchronous algorithms cannot avoid scenarios in which concurrent reading 1 ....

....reads writes to a location in one time slot. Models based on interleaving or rounds charge the same for an interleaving of reads writes to the same address as for an interleaving of reads writes to different addresses. 2 An exception is the erew variant of Gibbons asynchronous pram model [Gib89] which permits contention in 2 or writing occur. Since most existing parallel machines permit contention, but at a cost, the qrqw rule is a better choice for an asynchronous model than either the crcw or the erew rule. The qrqw rule can be incorporated into these previous models in a natural ....

[Article contains additional citation context not shown here]

P. B. Gibbons. A more practical PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 158--168, June 1989. Full version in The Asynchronous PRAM: A semi-synchronous model for shared memory MIMD machines, PhD thesis, U.C. Berkeley 1989. 18

....of the current generation of parallel machines. Thus, a number of alternative, intermediate models have been proposed and studied in recent years. These abstract models differ in what aspects of parallel machines are exposed. Some focus on dealing with asynchrony in a shared memory context (e.g. [8, 20, 21, 28, 32, 35, 49, 57, 61]) Others focus on accounting for the overheads in accessing the shared memory ( 2, 3, 25, 32, 41, 44, 52, 56] or in sending messages ( 5, 9, 10, 22, 23, 39, 53, 55, 69] Several models are primarily concerned with the memory hierarchy, especially disk I O ( 6, 62, 72] Others focus on ....

....and studied in recent years. These abstract models differ in what aspects of parallel machines are exposed. Some focus on dealing with asynchrony in a shared memory context (e.g. 8, 20, 21, 28, 32, 35, 49, 57, 61] Others focus on accounting for the overheads in accessing the shared memory ([2, 3, 25, 32, 41, 44, 52, 56]) or in sending messages ( 5, 9, 10, 22, 23, 39, 53, 55, 69] Several models are primarily concerned with the memory hierarchy, especially disk I O ( 6, 62, 72] Others focus on contention at the memory location ( 28, 36] or memory module ( 60, 7, 27] Finally, a few models incorporate ....

[Article contains additional citation context not shown here]

P. B. Gibbons. A more practical PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 158--168, June 1989. Full version in The Asynchronous PRAM: A semisynchronous model for shared memory MIMD machines, PhD thesis, U.C. Berkeley 1989.

....current generation of parallel machines. Thus, a number of alternative, intermediate models have been proposed and studied in the last eight years. These abstract models differ in what aspects of parallel machines are exposed. Some focus on dealing with asynchrony in a shared memory context (e.g. [6, 15, 16, 21, 25, 39, 47, 49]) Others focus on accounting for the overheads in accessing the shared memory ( 1, 2, 20, 25, 34, 36, 43, 46] or in sending messages ( 8, 9, 17, 18, 32, 44, 45, 55] Several models are primarily concerned with the memory hierarchy, especially disk I O ( 4, 50, 57] Others focus on contention ....

....and studied in the last eight years. These abstract models differ in what aspects of parallel machines are exposed. Some focus on dealing with asynchrony in a shared memory context (e.g. 6, 15, 16, 21, 25, 39, 47, 49] Others focus on accounting for the overheads in accessing the shared memory ([1, 2, 20, 25, 34, 36, 43, 46]) or in sending messages ( 8, 9, 17, 18, 32, 44, 45, 55] Several models are primarily concerned with the memory hierarchy, especially disk I O ( 4, 50, 57] Others focus on contention at the memory location ( 21, 30] or memory module ( 5] Finally, a few models incorporate powerful aggregate ....

[Article contains additional citation context not shown here]

P. B. Gibbons. A more practical PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 158--168, June 1989. Full version 10 in The Asynchronous PRAM: A semi-synchronous model for shared memory MIMD machines, PhD thesis, U.C. Berkeley 1989.

....as barriers can be constructed using shared memory reads, writes, and test sets. Analysis. In defining how algorithms are analyzed in the model, the qrqw asynchronous pram aims for a simple cost model that captures important realities of multiprocessors. As in Gibbons asynchronous pram model [Gib89] our cost model assumes that processors issue instructions at the same speed, as this is presumed to be the typical scenario in a multiprocessor. A local operation takes unit time. There is a FIFO queue associated with each memory location; only the request at the head of the queue is processed ....

....which permits unit time concurrent reading but applies the above queue rule for concurrent writing. The stronger crqw asynchronous pram model is used primarily to prove stronger lower bounds. Related work. A variety of asynchronous pram models have been studied in the literature (c.f. CZ89, Gib89, Nis90, And92, MPS92] These models account for contention in a manner most like a crcw pram, with no penalty assessed for large contention to a location. 2 An erew contention rule was not considered, 3 since most asynchronous algorithms cannot avoid scenarios in which concurrent reading or ....

[Article contains additional citation context not shown here]

P. B. Gibbons. A more practical PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 158--168, June 1989. Full version in The Asynchronous PRAM: A semi-synchronous model for shared memory MIMD machines, PhD thesis, U.C. Berkeley 1989.

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P. B. Gibbons. A More Practical PRAM Model. In Ist Symposium on Parallel Algorithms and Architectures, 1989.

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P.B. Gibbons, "A More Practical PRAM Model", Proc. of st ACM Symp. on Parallel Algorithms and Architectures, pp.158-168, June 1989

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P.B. Gibbons, "A More Practical PRAM Model", Proc. of st ACM Symp. on Parallel Algorithms and Architectures, pp.158-168, June 1989

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P. Gibbons. A More Practical PRAM Model. Proc. 1989.

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Gibbons, P.: A More Practical PRAM Model. Proc. of the 1989.

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P. Gibbons. A More Practical PRAM Model. Proceedings of the 1989 ACM Symposium on Parallel Algorithms and Architectures, pp. 158-168, 1989.

No context found.

P. Gibbons, "A More Practical PRAM Model," Proc. 1989 ACM Symp. on Parallel Algorithms and Architectures, pp. 158--168, 1989.

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