Richard Cole. The APRAM: Incorporating Asynchronyinto the PRAM Model. In Proceedings of the NSF - ARC Workshop on Opportunities and Constraints of Parallel Computing ([San89a]), pages 25--28, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....omitted from the main body of the paper appear in the appendix. 2 Model and de nitions We consider an asynchronous shared memory system where processors can work at arbitrarily varying paces. Our formal de nition is based on the Atomic Asynchronous Parallel System as presented by [5] cf. [11, 12, 15, 24, 28, 34]) The system consists of p processors, each has a dedicated local memory and a unique identi er from the set f1; pg, and any processor has access to shared memory. Any processor has a discrete local clock ranging over N = f1; 2; 3; g. A processor executes exactly one basic action ....

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. 2nd ACM Symposium on Parallel Algorithms and Architectures SPAA'89, (1989) 169-178

....and CRCW PRAM that account for differences in memory access conflict resolution schemes. The relationship between different basic PRAM models is discussed in [11] Other variations of the PRAM model have been introduced to model shared memory parallel computers that are asynchronous (APRAM model [7]) and semi asynchronous (PPRAM phase PRAM [13] Since most commercial parallel computers are a collection of processor memory pairs that operate asynchronously and communicate via an interconnection net work, efforts have been made to develop models for these computers that are more accurate ....

R. Cole and O. Zajicek, The APRAM: Incorporating asynchrony into the PRAM model, Proceedings ACM SPAA, 169-178, 1989.

....algorithms may fail to terminate in this case, the comparison should only be made in executions in which no process fails, i.e. in failure free executions. The time measure we use is the one introduced in [26, 27] and used to evaluate the time complexity of asynchronous algorithms, in, e.g. [3, 12, 34, 35, 44]. To summarize, we are interested in measuring the time cost imposed by the wait free property, as measured in terms of extra computation time in the most normal (failure free) case. In this paper, we address the general question by considering a specific problem the approximate agreement ....

.... com plexity is constant, i.e. it does not depend on the range of inputs or on e (Section 5) The algorithm uses a novel method of overcoming the uncertainty that is inherent in an asyn chronous environment, without resorting to synchronization points (cf. 22] or other waiting mechanisms (cf. [12]) this method involves ensuring that the two processes base their decisions on information that is approximately, but not exactly, the same. Next, using a powerful technique of integrating wait free (but slow) and non wait free (but. fast) algorithms, together with an O(log n) wait free input ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek, "The APRAM: Incorporating Asynchrony into the PRAM model," Proc. 1st A CM Syrup. on Parallel Algorithms and Architectures, 1989, pp. 169-178. 35

....left out from the main body of the paper appear in the appendix. 2 Model and definitions We consider an asynchronous shared memory system where processors can work at arbitrarily varying paces. Our formal definition is based on the Atomic Asynchronous Parallel System as presented by [4] cf. [11, 12, 15, 24, 27, 33]) The system consists of p processors each has a dedicated local memory and all processors have access to shared memory. Any processor has a discrete local clock ranging over N = f1; 2; 3; g. A processor executes exactly one basic action at any tick of the local clock unless the processor ....

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. 2nd ACM Symposium on Parallel Algorithms and Architectures SPAA'89, (1989) 169--178

....object is a strong synchronisation primitive that allows one to atomically read and update the contents of a shared memory object. Indeed, their synchronisation properties are so strong that it can be shown that these objects do not have a wait free implementation in the asynchronous PRAM model [CZ89,Her91] Preprint submitted to Elsevier Preprint 31st October 2000 On the other hand, shared memory objects whose operations either return the current state of the object or update the state of the object, but not both in a single operation, do admit wait free implementation in the asynchronous ....

Cole, R., and Zajiec, O. The APRAM: Incorporating asynchrony into the PRAM model. In Ann. Symp. on Parallel Algorithms and Architectures (Santa-Fe, NM, 1989), pp. 169-178.

....amount of time as a local computation step, whereas, in a real parallel computer architecture, a communication step is far more time consuming. There are several PRAM based models that include aspects of real parallel machines, such as latency [2, 3, 21] memory contention [14, 13] and asynchrony [6, 12]. The BSP model [22] and the LogP model [7, 9] are models of parallel computation that consist of a collection of processors that communicate using message passing. These models are more realistic, because they include several aspects of real parallel computers. Both models characterise a ....

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proceedings of the 1989.

....and realizable parallel computers is being bridged by current research. For example, memory access simulation in other architectures is the subject of a large body of literature surveyed in [98] for some recent work see [49, 87, 97] Computation on asynchronous PRAMs are the subject of [29, 31, 45, 75, 78]. The reliability of semiconductor memories has been thoroughly studied, and a survey can be found in [89] while the theory of error detecting and correcting codes is reviewed in [76] The fault tolerant issues of the interconnection networks used to integrate processors and memory modules are ....

....(as in [99] is exploited to our advantage. Asynchronous versions of the PRAM is a subject of recent research. Various means of relaxing the strict synchronization requirements of the standard PRAM have been used to show that efficient algorithms can be efficiently executed on asynchronous models [29, 31, 45, 78, 75]. A simple randomized algorithm that serves as a basis for simulating arbitrary PRAM algorithms on an asynchronous PRAM is presented by Martel et al. in [75] This randomized asynchronous simulation has very good expected performance for the Write All problem when the adversary is off line. Other ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek, "The APRAM: Incorporating Asynchrony into the PRAM Model," in Proc. of the 1989.

....memory accesses are unit cost and that synchronization is unnecessary (because processors run in lockstep) These assumptions simplify analysis, but do not reflect real computers, particularly those with caches. For this reason, PRAM extensions model non uniform memory and processor asynchrony [3, 10, 33, 20]. The new models are more descriptive and complex than traditional PRAM models, but still do not accurately describe cache coherent parallel computers. Perhaps this paper will help inspire PRAM extensions that describe this important type of computers. Culler et al. described another model of ....

Richard Cole and Ofer Zajicek. The APRAM: Incorporating Asynchrony into the PRAM Model. In Proceedings of the First ACM Symposium on Parallel Algorithms and Architectures (SPAA), pages 169 178, June 1989.

....balancing the tasks. Our implementation also implies time bounds of O(gw p d(T s ( p) L) on the BSP [30] where g is the BSP gap parameter and is inversely related to bandwidth and L is the BSP periodicity parameter and is related to latency, O(w p d lg p) on an asynchronous EREW PRAM [20], and O(w p d) on the EREW scan model [6] The conversion to linear code is a simple manipulation that can be done by a compiler. Although this conversion can potentially increase the work and or depth of a computation, it does not for any of the algorithms described in this paper. In fact, ....

....written before they can be copied. 234 G. E. Blelloch and M. Reid Miller (all prefix sums) operation. The bounds we prove on the scan model imply bounds of O(w p d lg p) time on the plain EREW PRAM, O(gw p d(T s L) on the BSP [30] and O(w p d lg p) on an asynchronous EREW PRAM [20] using standard simulations. Lemma 4.1 (Implementation of Futures) Any linearized future based computation with w work and d depth can be simulated on an EREW scan model in O(w p d) time. Proof. In the following discussion we say that an action (node in the computation DAG) is ready if all ....

R. Cole and O. Zajicek. The APRAM: incorporating asynchrony into the PRAM model. In Proceedings of the

....is a convenient model for which numerous ecient algorithms have been developed [9, 11, 20] However, pram makes assumptions that, given the current state of technology, make it dicult for it to be implemented as a scalable architecture. A number of works address and deal with this problem (e.g. [6, 7, 12, 17, 26, 25, 28, 29, 32]) Some approaches preserve pram as a model for algorithm designers and provide algorithmic simulations of pram algorithms on other platforms. It has been shown that solutions for a particular problem can be used as building blocks in constructing such simulations (e.g. 8, 21, 26, 30] This ....

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. Proc. of the

....term, because of timing uncertainties introduced by variations in instruction complexity, page faults, cache misses, and operating system activities such as preemption or swapping. A number of researchers have noted this mismatch, and have proposed the asynchronous PRAM model as an alternative [16, 17, 21, 41]. In this model, asynchronous processes communicate by applying atomic read and write operations to the shared memory 2 . Techniques for implementing these memory locations, often called atomic registers, have also received considerable attention [13, 14, 32, 35, 40, 43, 44] Much of the work ....

....objects, implying that despite the weakness of the model, certain problems do have wait free solutions. Perhaps the most general contribution is to raise basic questions about the value of the asynchronous PRAM model. Although some synchronous PRAM algorithms can be adapted to asynchronous PRAM [16, 17, 21, 41], our results show that there is little hope of constructing useful highly concurrent long lived data structures in this model. Fortunately, however, one can argue that asynchronous PRAM is an incomplete re ection of current practice. Starting with the IBM System 370 architecture [30] in the ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek. The APRAM: incorporating asynchrony into the PRAM model. In Proceedings of the Symposium on Parallel Algorithms and Architectures, pages 169-178, Santa Fe, NM, June 1989.

....interval over which every process which has not yet terminated executes at least one step, then counting the number of rounds provides one way of measuring the time complexity of asynchronous systems. This measure is called round complexity of an asynchronous computation. The reader is referred to [14] for further details. The formal speci cation of the symmetry breaking problem for the case of N processes is as follows. Every process has a special private variable called id that is unde ned initially (a special symbol denotes an unde ned value) and is assigned at most once by the process. A ....

....time EN (x N ) of the synchronous algorithm in Figure 2 is O(N 2 ) 23 6.2 Asynchronous Case In this section we analyze the time and space requirements of our asynchronous algorithm for each of three system models. We analyze the time required by our algorithm in terms of its round complexity [14]. A round is a minimal time interval over which every process which has not yet terminated executes at least one step. The round complexity of of an asynchronous algorithm for a given input is the maximum number of rounds over all possible computations for that input. Our initial time analysis is ....

Cole, R., and O. Zajicek, The APRAM: Incorporating Asynchrony into the PRAM Model, Proceedings of the

....is a convenient model for which numerous ecient algorithms have been developed [10, 12, 21] However, pram makes assumptions that, given the current state of technology, make it dicult for it to be implemented as a scalable architecture. A number of works address and deal with this problem (e.g. [6, 8, 13, 18, 29, 28, 31, 32, 35]) Some approaches preserve pram as a model for algorithm designers and provide algorithmic simulations of pram algorithms on other platforms. It has been shown that solutions for a particular problem can be used as building blocks in constructing such simulations (e.g. 9, 23, 29, 33] This ....

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. Proc. of the 1989 ACM Symp. on Parallel Algorithms and Architectures (1989) 170-178

....However, as the XMT model is more resilient to unpredictable data access time, these algorithms are able to obtain good speedups. 9. Related work XMT has tried to build on available technologies to the extent possible. The relaxation in the synchrony of PRAM algorithms is related to the work of [CZ89] on asynchronous PRAMs. Basic insights concerning the use of a prefix sum like primitive go back to the Fetch and Add or Fetchand Increment [FG91] primitives (cf. AG94] Another design point for on chip parallelism is that occupied by chip multiprocessors (CMP) where independent processing ....

R. Cole and O. Zajicek, "The APRAM: incorporating asynchrony into the PRAM model," Proc. 1st ACM-SPAA, pp. 169-178, 1989.

....problematic for the PCS model where processing units (machines or processes) may be arbitrarily snatched or get started by the external system. We propose a novel asynchronous complexity criterion which is simpler and more adequate for the PCS model than the previously suggested criteria ([15, 14, 6, 1, 2]) With our criterion, the adversary is not restricted and can choose the worst execution order. Consequently, any PCS algorithm must be nonblocking. Thus we must allow the use of non blocking synchronization primitives such as Fetch and Add [5] or Test and set in the PCS model. The proposed ....

....for the PRAM model which is the relevant model for this work. Gibbons [6] introduces a model in which the computation is divided into phases which are separated by barrier synchronizations. The length of a phase is the length of the longest computation in it. The APRAM of Cole and Zajicek [1] does not require any synchronization, but the algorithm is restricted to working in rounds where in each processor must be advanced by at least one step. The execution time is the sum of maximal steps of a processor in every round. The power of the adversary to choose the worst execution order ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Symp. Parallel Algorithms & Architectures, pages 169-178, Jun 1989.

....Figure 7. This can be attributed to the XMT architecture design, which relies on a high bandwidth, scalable on chip memory system. 7. Related work XMT has tried to build on available technologies to the extent possible. The relaxation in the synchrony of PRAM algorithms is related to the work of [CZ89] on asynchronous PRAMs. Basic insights concerning the use of a prefix sum like primitive go back to the Fetch andAdd or Fetch and Increment [FG91] primitives (cf. AG94] MIT s Cilk [FLR98] provides a multi threaded programming interface and execution model. There are two important differences ....

R. Cole and O. Zajicek, "The APRAM: incorporating asynchrony into the PRAM model," Proc. 1st ACM-SPAA, pp. 169-178, 1989.

....The PRAM model assumesconflict free accessesto shared memory (assigning unit cost for memory accesses) and zero cost for synchronization. The PRAM model has been augmented with additional parameters to account for memory access latency [4] memory access conflicts [5] and cost of synchronization [15, 9]. The Bulk Synchronous Parallel (BSP) model [28] and the LogP model [11] are departures from the PRAM models, and attempt to realistically bridge the gap between theory and practice. Similarly, considerable effort has been expended in the area of performance evaluation in developing simple ....

R. Cole and O. Zajicek. The APRAM: Incorporating Asynchrony into the PRAM Model. In Proceedings of the First Annual ACM Symposium on Parallel Algorithms and Architectures, pages 169-- 178, 1989.

....processors such as the TMC CM 2 or the MasPar MP 1 are programmed using data parallel operations and barrier synchronization. Families of abstract computational models for these classes of synchronous and asynchronous sharedmemory machines may be found in the PRAM and APRAM respectively [CZ89] The proliferation of languages following different concurrent programming paradigms targeting different architectures, together with the emergence of heterogeneous systems and mixed mode architectures, pose problems for software development by increasing the complexity of programming and by ....

....rates as probability functions that is, giving a fuzzy rate as a function from rates to expected probability yielding a probabilistic rate control. The semantics then associates, for each admissible execution history, a probability in a manner analogous to that for variable speed APRAM s [CZ89] The rate construct proves advantageous in several ways. The specification of expected rate of progress is interpreted as a scheduling directive that, when simulating execution of prototypes, allows experimentation to predict real time behavior. The rate construct can also be viewed as ....

R. Cole and O. Zajicek, "The APRAM: Incorporating asynchrony into the PRAM model," in Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pp. 169--178, ACM, 1989.

....has spurred the development of several extensions of the PRAM which attempt to make the model more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [Gib89] and APRAM [CZ89] communication costs such as network latency and bandwidth (e.g. the LPRAM [ACS90] Postal Model [BNK92] BSP [Val90] and LogP [CKP 93] and memory hierarchy, reflecting the effects of multileveled memory such as differing access times for registers, local cache, main memory, and disk ....

....be assigned log B processors. Therefore the time to compute one set in each stage is O(B log B) log B, 7 which is equal to O(B) The total time, including the synchronization cost after each stage, is O(B log N= log B) 4.1. 2 APRAM The Asynchronous PRAM (APRAM) is a fully asynchronous model [CZ89, CZ90] The APRAM model consists of a global shared memory and a set of processes with their own local memories. The basic operations executed by the APRAM process are called events. An APRAM computation is denoted as the set of possible serializations of events executed by the processes. A ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek, "The APRAM: Incorporating asynchrony into the PRAM model," in Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pp. 169-- 178, ACM, 1989.

.... with languages that support shared variables with access exclusion and synchronization mechanisms like monitors, such as found in Concurrent Pascal, or with semaphores such as found in Mach [BRS 85] A theoretical model for these asynchronous shared memory machines is found in the APRAM [CZ89] ffl Highly parallel processors Applications for distributed memory machines such as the CM 2 or the NCube are programmed using data parallel operations and barrier synchronization. Languages used to program machine designs such as the CM and the UltraComputer include specific features that ....

R. Cole and O. Zajicek, "The APRAM: Incorporating asynchrony into the PRAM model," in Proceedings of the First ACM Symposium on Parallel Algorithms and Architectures, pp. 169-- 178, ACM Press, 1989.

....pram cost measure appears in Section 6. 2 The QRQW Asynchronous PRAM In this section, we present the definition of the qrqw asynchronous pram model, and some observations on the algorithmic power of the model. A variety of asynchronous pram models have been studied in the literature (c.f. CZ89, Gib89, Nis90, And92, MPS92] These models account for contention in a manner most like a crcw pram, with no penalty assessed for large contention to a location. 1 An erew contention rule was not considered, 2 since most asynchronous algorithms cannot avoid scenarios in which concurrent ....

....processors and in processing memory requests, and the qrqw asynchronous pram reflects this reality. Most asynchronous shared memory models of computation assume that a processor can have at most one pending memory request at a time: there is no pipelining of memory requests by a processor (e.g. CZ89, Nis90, And92, MPS92, DHW93] 3 On the other hand, high performance shared memory machines such as the Tera MTA permit the pipelining of memory accesses by a processor, in order to amortize the round trip time to memory over a collection of accesses. In the qrqw asynchronous pram, pipelining ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 169--178, June 1989.

....problem has spurred the development of several extensions of the PRAM which attempt to make the model more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [33] and APRAM [18]) communication costs such as network latency and bandwidth (e.g. the LPRAM [4] the Postal Model [9] BSP [82] LogP [25] and memory hierarchy such as the models discussed in the previous paragraph. In practice, both the performance of inter connection networks which connect processors ....

....has spurred the development of several extensions of the PRAM which attempt to make the model 17 18 more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [33] and APRAM [18]) communication costs such as network latency and bandwidth (e.g. the LPRAM [4] Postal Model [9] BSP [82] and LogP [25] and memory hierarchy, reflecting the effects of multileveled memory such as differing access times for registers, local cache, main memory, and disk I O (e.g. the P HMM ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proc. of the Symposium on Parallel Arch. and Algorithms, pages 169--178, Santa Fe, New Mexico, June 1989.

....has spurred the development of several extensions of the PRAM which attempt to make the model more practical while still preserving much of its simplicity. The variations extend the PRAM to incorporate realistic aspects such as asynchrony of processes (e.g. the Phase PRAM [Gib89] and APRAM [CZ89] communication costs such as network latency and bandwidth (e.g. the LPRAM [ACS89] Postal Model [BNK92] BSP [Val90] and LogP [CKP 93] and memory hierarchy, reflecting the effects of multileveled memory such as differing access times for registers, local cache, main memory and disk I O ....

....of a Phase PRAM algorithm design for FFT computation; an example may be found in [Gib89] It is worth noting that a variant of the Phase PRAM, the Phase LPRAM model, accounts as well for the cost of communication latency. APRAM. The Asynchronous PRAM (APRAM) is a fully asynchronous model [CZ89] The APRAM model consists of a global shared memory and a set of processes with their own local memories. The basic operations executed by the APRAM process are called events. An APRAM computation is denoted as the set of possible serializations of events executed by the processes. A virtual ....

[Article contains additional citation context not shown here]

R. Cole and O. Zajicek, "The APRAM: Incorporating asynchrony into the PRAM model," in Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pp. 169--178, ACM, 1989.

....as probability variables that is, giving rate constraints as a function from rates to expected probability yielding a probabilistic rate control. The semantics then associates, for each admissible execution history, a probability in a manner analogous to that for variable speed APRAM s [CZ89] The rate construct proves advantageous in several ways. The specification of expected rate of progress is interpreted as a scheduling directive that, when simulating execution of prototypes, allows experimentation to predict real time behavior. The rate construct can also be viewed as ....

R. Cole and O. Zajicek, "The APRAM: Incorporating asynchrony into the PRAM model," in Proc. of the First ACM Symp. on Parallel Algorithms and Architectures, pp. 169--178, ACM Press, 1989.

....is a strong synchronization primitive that allows one to atomically read and update the contents of shared memory register. Indeed, their synchronization properties are so strong that it can be shown that these registers do not have a wait free implementation in the asynchronous PRAM model [CZ89, Her91]. In this paper we are concerned with weaker RMW registers, where an operation P can only change part of the state modeled by the state transition mapping # P ( and return a function of the old contents (possibly masking information) modeled by the output mapping # P ( Herlihy has ....

COLE, R., AND ZAJIEC, O. The APRAM: Incorporating asynchrony into the PRAM model. In SPAA (Santa-Fe, NM, 1989), pp. 169--178.

....model; these bounds are closer to the total amount of actual work required over the amount of available parallelism, than appears to be possible without reduced synchrony. The second feature is the departure from the lockstep structure of most PRAM related models (notable exceptions include [G89] [CZ89], or bulksynchronous parallelism, BSP [Va90] which was motivated by the following insight: although 9 PRAM algorithms are synchronous, their semantics allows some slack in the synchrony requirements of their (more refined) instruction code. This slack translates into reduced synchrony, as per ....

....pairs at the algorithmic level (since Join is the main synchronization instruction) This discussion gives us an opportunity to relate to other works. Designing (possibly different) parallel algorithms which are less synchronous was considered in the context of the Phase PRAM of [G89] APRAM [CZ89], or bulk synchronous parallelism (BSP) Va90] However, our emphasis in the asynchronous mode is different. We remain with the same parallel algorithm; its proper implementation in the instruction set level (which is more fine grained than the algorithm level) could need less tight ....

R. Cole and O. Zajicek. The APRAM: incorporating asynchrony into the PRAM model. Parallelism: In Proc. 1st ACM-SPAA, 1989, 169--178.

....of the current generation of parallel machines. Thus, a number of alternative, intermediate models have been proposed and studied in recent years. These abstract models differ in what aspects of parallel machines are exposed. Some focus on dealing with asynchrony in a shared memory context (e.g. [8, 20, 21, 28, 32, 35, 49, 57, 61]) Others focus on accounting for the overheads in accessing the shared memory ( 2, 3, 25, 32, 41, 44, 52, 56] or in sending messages ( 5, 9, 10, 22, 23, 39, 53, 55, 69] Several models are primarily concerned with the memory hierarchy, especially disk I O ( 6, 62, 72] Others focus on ....

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 169--178, June 1989.

....of better techniques and tools for performance prediction. Models and resource metrics for parallel computation. In response to the first need there have been proposed a variety of models which extend the PRAM to incorporate realistic aspects suchasasynchrony of processes (e.g. the APRAM [9]) communication costs, such as network latency and bandwidth restrictions (e.g. the LogP model [10] and memory hierarchy, reflecting the effects of multileveled memory such as differing access times for registers, local cache, main memory and disk I O (e.g. the P HMM [23] The most prevalent ....

Richard Cole and Ofer Zajicek. The APRAM: Incorporating asynchronyinto the PRAM model. In Proc. of the First ACM SymposiumonParallel Algorithms and Architectures, pages 169--178. ACM Press, 1989.

....with networks whose comparator gates may be faulty but whose connections do not fail. This is akin to a computation model where processors do not fail, but may sometimes return the wrong result for a comparison. Related work has also been done on asynchronous computing models. Cole and Zajicek [19] proposed the APRAM model for designing parallel algorithms to work in an asynchronous setting. Zhou et al. 44] present a sorting algorithm for asynchronous machines that is not wait free. Neither is the recent sorting algorithm of Gibbons et al. 24] for the QRQW asynchronous PRAM. This ....

Cole, R., and Zajicek, O. The APRAM: Incorporating asynchrony into the PRAM model. In Proceedings of the 1st Annual ACM Symposium on Parallel Algorithms and Architectures (Santa Fe, NM, June 1989), A.-S. ACM-SIGARCH, Ed., ACM Press, pp. 169--178.

....current generation of parallel machines. Thus, a number of alternative, intermediate models have been proposed and studied in the last eight years. These abstract models differ in what aspects of parallel machines are exposed. Some focus on dealing with asynchrony in a shared memory context (e.g. [6, 15, 16, 21, 25, 39, 47, 49]) Others focus on accounting for the overheads in accessing the shared memory ( 1, 2, 20, 25, 34, 36, 43, 46] or in sending messages ( 8, 9, 17, 18, 32, 44, 45, 55] Several models are primarily concerned with the memory hierarchy, especially disk I O ( 4, 50, 57] Others focus on contention ....

....messages. The underlying communication network is modeled using a series of parameters reflecting, e.g. the bandwidth and latency of the network. Many of these models either explicitly or implicitly support a distributed memory abstraction as well. Asynchronous shared memory models (cf. [6, 15, 16, 21, 25, 29, 39, 40, 47, 49]) consist of a collection of asynchronous processors communicating by reading and writing locations in a shared memory. Memory hierarchy models (cf. 4, 50, 57] focus on accounting for various levels of the storage hierarchy. Given this plethora of models, it is natural to seek to distinguish a ....

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms andArchitectures, pages 169--178, June 1989.

....with networks whose comparator gates may be faulty but whose connections do not fail. This is akin to a computation model where processors do not fail, but may sometimes return the wrong result for a comparison. Related work has also been done on asynchronous computing models. Cole and Zajicek [12] proposed the APRAM model for designing parallel algorithms to work in an asynchronous setting. Zhou et al. 34] present a sorting algorithm for asynchronous machines that is not wait free. Neither is the recent sorting algorithm of Gibbons et al. 15] for the QRQW asynchronous PRAM. While these ....

Cole, R., and Zajicek, O. The APRAM: Incorporating asynchrony into the PRAM model. In Proceedings of the 1st Annual ACM Symposium on Parallel Algorithms and Architectures (Santa Fe, NM, June 1989), A.-S. ACM-SIGARCH, Ed., ACM Press, pp. 169--178.

....cross chip interconnect delays. 5 Related Work First of all, we should emphasize that we have not invented parallel computing with XMT. We have tried to build on available technologies to the extent possible. The relaxation in the synchrony of PRAM algorithms is related to the works of [7] and [15] on asynchronous PRAMs. The high level language we used for XMT builds on Fork95 and its previous versions developed at the U. Saarbrucken, Germany, see [20] and [21] Basic insights concerning the use of a prefix sum like primitive go back to the Fetch and Add [16] or Fetch and Increment ....

R. Cole and O. Zajicek, "The APRAM: incorporating asynchrony into the PRAM model," Proc. 1st ACM-SPAA, pp. 169-178, 1989.

....and analysis. These models try to hide hardware details from the programmer, providing a simplified view of the machine. The utility of such models towards developing efficient algorithms for actual machines, depends on the closeness of the model to the actual machine. Several machine models [2, 3, 27, 14, 59, 17] have been proposed over the years to bridge the gap between the theoretical abstractions and the hardware. But, a complex model that incorporates all the hardware details would no longer limit the degrees of freedom to a tractable level, precluding its ease of use for algorithm development and ....

....a transfer rate to access subsequent words. Mehlhorn et al. 3] use a model called the Module Parallel Computer (MPC) which incorporates contention for simultaneous accesses by different processors to the same memory module. The implicit synchronization assumption in PRAMs is removed in [27] and [14]. In their models, the processors execute asynchronously, with explicit synchronization steps to enforce synchrony when needed. Valiant [59] introduces the Bulk Synchronous Parallel (BSP) model which has: a number of components, each performing processing and or memory functions; a router that ....

R. Cole and O. Zajicek. The APRAM: Incorporating Asynchrony into the PRAM Model. In Proceedings of the First Annual ACM Symposium on Parallel Algorithms and Architectures, pages 169--178, 1989.

....of parallel computers to be able to develop cost effective parallel computers in the future. Several suggestions have been made to fill the gap between the theoretical algorithms and the existing parallel computers. Some examples of the proposed models are BSP [9] LogP [3] Y PRAM [8] APRAM [2], and Phase PRAM [4] Each of these models provides a set of restrictions and other features which should make the model more realistic. Some of the models are, however, still rather theoretical, and do not necessarily provide good enough connection between the parallel programming and parallel ....

Cole R., Zajicek O.: The APRAM: Incorporating Asynchrony into the PRAM Model. In Proceedings of 1st ACM Symposium on Parallel Algorithms and Architectures, pages 169-178, 1989.

....and barrier synchronization. Families of abstract computational models for these classes of synchronous and asynchronous shared memory machines z This work was supported under DARPA SISTO contract N00014 91 C 0114 administered through ONR. may be found in the PRAM and APRAM respectively [CZ89] The proliferation of languages following different concurrent programming paradigms targeting different architectures, together with the emergence of heterogeneous systems and mixed mode architectures, pose problems for the development of parallel software. The diversity of languages and ....

R. Cole and O. Zajicek, "The APRAM: Incorporating asynchrony into the PRAM model," in Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pp. 169--178, ACM, 1989.

....avoid [GMR96] We use the asynchronous version of the QRQW PRAM, where each memory location has a FIFO queue, memory requests must first traverse the queue, and each memory location handles one item per time step. Processors behave asynchronously, and this can be modeled in several different ways: [CZ89], CZ90] Nis90] Examples of asynchronous machines that conform well to the QRQW rule are the Kendall Square KSR 1, the Tera Computer, and the Stanford DASH [GMR94a] The existing analysis of asynchronous QRQW algorithms [GMR96] has taken the following approach: the algorithm must work correctly ....

R. Cole, O. Zajicek. The APRAM: Incorporating Asynchrony into the PRAM Model In Proc. 1 st ACM Symposium on Parallel Algorithms and Architectures pp. 169-178, 1989.

....Suitable parameterization allows for straightforward estimates of run times; such estimations are the more accurate, the more the particular parallel hardware fits the model used. In our case, the programming model is the Asynchronous PRAM introduced in the parallel theory community in 1989 [13, 9, 10]. An Asynchronous PRAM (see Fig. 1) is a MIMD parallel computer with a sequentially consistent shared memory. Each processor runs with its own clock. No assumptions are made on uniformity of shared memory access times. Thus, much more than for a true PRAM, the programmer must explicitly take care ....

R. Cole, O. Zajicek. The APRAM: Incorporating Asynchrony into the PRAM model. Proc. 1st Ann. ACM Symp. on Par. Algorithms and Architectures, pp. 169--178, 1989.

....not truly general purpose. Dept. of Computer Sciences, University of Texas at Austin, Austin, TX 78712. email: vlr cs.utexas.edu. This work was supported in part by NSF grant CCR GER 90 23059. Thus is not surprising that a variety of other models have been proposed in the literature, e.g. [2, 5, 6, 7, 9, 13, 15, 18, 23, 29, 32, 34, 35, 38, 40, 45, 46]) to address specific drawbacks of the pram although none of these are general purpose models. In recent years, distributed memory models that characterize the interconnection network abstractly by parameters that capture its performance have gained much attention. An early work along these lines ....

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 169--178, June 1989.

....models confirm that the PAR model s advantages can be obtained at a reasonable cost. 1. Introduction Though the PRAM is a widely studied model of parallel computation, it is not universally accepted; several researchers have sought a replacement that overcomes some of the PRAM s drawbacks [1, 4, 5, 8, 11, 12]. The PRAM is a low level model of parallel computation. Although it is one step removed from specific hardware models, the PRAM is still a processor based model. A PRAM program must specify both processor execution and processor scheduling. The requirement to explicitly schedule processors ....

....requirement to explicitly schedule processors increases the difficulty of exposing the natural parallelism in a problem solution. The PRAM is a synchronous machine. However, many researchers argue that any massively parallel architecture must be asynchronous in order to realize maximum efficiency [4, 5, 8, 11, 12]. Research supported in part by a research grant from the Natural Sciences and Engineering Research Council y Research supported in part by a postgraduate scholarship from the Natural Sciences and Engineering Research Council Because lock step synchronization is too expensive, realistic ....

Richard Cole and Ofer Zajicek, The APRAM: Incorporating asynchrony into the PRAM model, Proceedings of the 1st Annual ACM Symposium on Parallel Algorithms and Architectures, 1989, pp. 169--178.

....parallel machine is much more complex. The problems due to faults and asynchrony in parallel computing have been recognized for some time by the algorithms community. In this paper we are not able to present in any detail the earlier formal work done in this area; for typical examples, see [4], 10] and [11] However, the approach taken there did not address the general problem of reliable computing under the most general assumptions on the parallel computers. For instance, the results presented in [10] for the case of fail stop processors and in [11] for the case of asynchronous ....

R. Cole and O. Zajicek, "The APRAM: Incorporating Asynchrony into the PRAM Model," Proc. 1989 ACM Symp. on Parallel Algorithms and Architectures, 170--178, 1989.

No context found.

Richard Cole. The APRAM: Incorporating Asynchronyinto the PRAM Model. In Proceedings of the NSF - ARC Workshop on Opportunities and Constraints of Parallel Computing ([San89a]), pages 25--28, 1989.

No context found.

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. 2nd ACM Symposium on Parallel Algorithms and Architectures SPAA'89, (1989) 169--178

No context found.

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. 2nd ACM Symposium on Parallel Algorithms and Architectures SPAA'89, (1989) 169--178

No context found.

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. 2nd ACM Symposium on Parallel Algorithms and Architectures SPAA'89, (1989) 169--178

No context found.

R. Cole and O. Zajicek. The APRAM: Incorporating Asynchrony into the PRAM Model. In Proceedings of the 1st Annual ACM Symposium on Parallel Algorithms and Architectures, pages 158--168, 1989.

No context found.

R. Cole, O. Zajicek, The APRAM: Incorporating Asynchrony into the PRAM Model, Proc. of STOC (1989).

No context found.

Cole, R., Zajicek, O.: The APRAM: Incorporating Asynchrony into the PRAM Model. Proc. of the 1989.

No context found.

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 169--178, June 1989.

No context found.

R. Cole and O. Zajicek. The APRAM: Incorporating asynchrony into the PRAM model. In Proc. 1st ACM Symp. on Parallel Algorithms and Architectures, pages 169--178, June 1989.

No context found.

:146#158, 1989. #CZ89# R. Cole and O. Zajicek, #The APRAM: Incorporating Asynchrony into the PRAM Model," Proc. 1989 ACM Symp. on Parallel Algorithms and Architectures,

First 50 documents  Next 50

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC