K. D. Cooper and P. Schileke, "Non-local instruction scheduling with limited code growth," in Proc. ACM SIGPLAN Workshop Languages, Compilation, and Tools Embedded Systems, 1998, pp. 193--207.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....there can be no wasted space. Put more succinctly, everything from chip design to on board memory must take as little space as possible. To this end, a few approaches to limiting the amount of memory needed to hold executable code have surfaced. Some techniques look at instruction scheduling [CS98, CSS99] and its effect on target code size. Other techniques employ some form of pattern matching [CM99, LDK99] to eliminate regions of repeated code. A third genre of technique attempts to physically compress the target code [LW98] to save on precious memory space. An attempt to limit target ....

....some form of pattern matching [CM99, LDK99] to eliminate regions of repeated code. A third genre of technique attempts to physically compress the target code [LW98] to save on precious memory space. An attempt to limit target code growth via efficient instruction scheduling was introduced by [CS98] This technique merely tries to repair the damage (the increase in code space requirements) normally done by instruction scheduling optimization (e.g. finding another sequence of instructions that minimizes the number of nop instructions) This is done by scheduling larger regions of code ....

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Keith D. Cooper and Philip J. Schielke. Nonlocal instruction scheduling with limited code growth. In ACM Proceedings of the SIGPLAN

....and dead code elimination) several optimizations like loop unrolling, procedure in lining etc. result in a speed size tradeo . Due to tight constraints on memory and real time response, both code size and speed are very important for the application speci c instruction processors (ASIPs) [8]. ASIPs o er new challenges to optimizing compilers and new approaches and paradigms are needed to generate ecient and compact code. DSPs form an important category of embedded ASIPs. Traditional compilers do not provide support for the specialized features of the DSPs by means of ....

....on dynamic instruction count for mix t 27 Accepted for publication in IEEE Trans. Computer Aided Design (TCAD) 2000 generation of compensation code. Region scheduling was proposed by Gupta and So a [20] that signi cantly improves performance through duplication. Recently, Cooper and Schielke [8] have proposed two code scheduling methods: extended basic block scheduling (EBBS) and dominator path scheduling (DPS) to exploit ILP in a global scope. Kemal Ebcioglu et al. 12] have designed a set of new algorithm for reducing path length and removing stalls due to branches, namely speculative ....

K. D. Cooper and P. Schielke. Non-local instruction scheduling with limited code growth. In ACM SIGPLAN Workshop on Languauges, Compilation and Tools for Embedded Systems, pages 193-207, June 1998.

....DSP compilers (such as SPAM [14] delay storage al location of variables from the front end to after the code selection phase. After code generation when the sequence of variable accesses is known, storage assignment is performed as a separate code optimization pass. A number of approaches [6, 4, 3, 17, 15] based on instruction selection and scheduling have been proposed to improve code size but do not attempt the problem of code compaction in relation to storage assignment. In this work, we focus on the problem of storage assignment for improving code size. The storage assignment problem was rst ....

K. Cooper and P. Schielke. Non-Local Instruction Scheduling with Limited Code Growth. In Proceedings of Languages, Compilers and Tools for Embedded Systems '98 (LCTES'98), pages 193-207, June 1998.

....elimination and dead code elimination) several optimizations like loop unrolling, procedure inlining etc. result in a speed size tradeoff. Due to tight constraints on memory and real time response, code size and speed are very important for the application specific instruction processors (ASIPs) [8]. ASIPs offer new challenges to optimizing compilers and new approaches and paradigms are needed to generate efficient and compact code. DSPs form an important category of embedded ASIPs. Traditional compilers fail to provide support for the specialized features of the DSPs by means of ....

....criticisms of trace scheduling is code growth; however, as shown by Freudenberger et al. 14] there are ways to avoid generation of compensation code. Region scheduling was proposed by Gupta and Soffa [17] that significantly improves performance through duplication. Recently, Cooper and Schielke [8] have proposed two code scheduling methods: extended basic block scheduling (EBBS) and dominator path scheduling (DPS) to exploit ILP in a global scope. However, these techniques do not deal with the issue of complex and irregular data paths which is one of the significant bottlenecks especially ....

K. D. Cooper and P. Schielke. Non-local instruction scheduling with limited code growth. In ACM SIGPLAN Workshop LCTES '98, pp. 193--207, June 1998.

....execution speed performance requirements by exploiting ILP, they must be able to deliver this performance under tight memory requirements. Thus the issue of code density is extremely important in such systems. The code growth that accompanies existing scheduling techniques may not be acceptable [54, 67, 43]. Jain et al. 93] developed a code motion framework to exploit ILP on TMS 320C2x. However, this framework is limited only to a basic block. Also the existing scheduling techniques do not deal with the issue of complex data paths between functional units that are typically found in DSPs [14] and ....

....that the SOA problem is equivalent to the maximum weighted path covering (MWPC) problem and proved that it is NP complete. Recently, Rao et al. 147] have derived a sequence of systematic program transformations when applied solves the problem efficiently for most cases. A number of approaches [43, 15, 14, 166, 165] based on instruction selection and scheduling have been proposed to improve code size but they do not address the problem of code compaction in relation to storage assignment. 4 Shared Memory Parallelism In this section, we summarize past work, the current state of the art, and future directions ....

K. Cooper and P. Schielke, "Non-Local Instruction Scheduling with Limited Code Growth," Proc. of Languages, Compilers and Tools for Embedded Systems, pages 193--207, June 1998.

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K. D. Cooper and P. Schileke, "Non-local instruction scheduling with limited code growth," in Proc. ACM SIGPLAN Workshop Languages, Compilation, and Tools Embedded Systems, 1998, pp. 193--207.

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