Michel Dubois, Christoph Scheurich, and Fay'e A. Briggs. Synchronization, coherence, and event ordering in multiprocessors. IEEE Computer, 21(2):9--21, February 1988. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Tolerating Latency Through Software-Controlled Prefetching in.. - Mowry, Gupta (1991) (232 citations) (Correct)
....high processor utilization in large scale shared memory multiprocessors. A number of different solutions have been proposed. For example, many recent multiprocessors [2, 13, 17] provide caches to help reduce the latency seen by the processor. More recently, weaker memory consistency models [1, 4, 6, 7] have been proposed that allow buffering and pipelining of memory references to hide latency. Still another technique is the use of processors with multiple hardware contexts [2, 10, 11, 26] These processors tolerate latency by switching from one context to another when they encounter a high ....
Michel Dubois, Christoph Scheurich, and Fay6 A. Briggs. Synchronization, coherence, and event ordering in multiprocessors. Computer, 21(2):9-21, February 1988.
An Interaction of Coherence Protocols and Memory Consistency.. - Shi, Hu, Tang (1997) Self-citation (Coherence) (Correct)
....definition, the role of coherence is to ensure that the coherent view of the given memory location by multiple processors. Ordering of events describes the happen sequence of memory events issued by each processor. Here, we use memory events to represent the read and store operation to the memory[17]. Memory consistency model is the logical sum of coherence protocol and event ordering in each processor. For example, sequential consistency, defined by Lamport in 1979[32] can be viewed as two conditions[2] 1. all memory access appear to execute automatically in some total order. 2. all ....
....graph for write invalidated based multiple writer protocol for LRC. 3 Although in [24] the authors didn t tell us the multiple writer protocol is adopted, from the examples shown in that paper we deduce that scope consistency uses multiple writer protocol too. 4 Related Works Dubios et.al in [17] analyzed the relationship between synchronization, coherence and event ordering. Although they separated the concepts of coherence and event ordering, they didn t present the relationship between them, and they equalized event ordering with memory consistency model, which is different from our ....
Michel Dubios and Christoph Scheurich. Synchronization, Coherence, and Event Ordering in Multiprocessors. in IEEE Transactions on Computer, Volume 21, Number 2. February 1988. pp.9-21.
AdaptiveSoftware Cache Managementfor - Distributed Shared Memory (Correct)
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Michel Dubois, Christoph Scheurich, and Fay'e A. Briggs. Synchronization, coherence, and event ordering in multiprocessors. IEEE Computer, 21(2):9--21, February 1988.
Compiler Analysis to Implement Point-to-Point Synchronization in.. - Nguyen (1993) (3 citations) (Correct)
No context found.
Michel Dubois, Christoph Scheurich, and Faye A. Briggs. Synchronization, co- herence, and event ordering in multiprocessors. Computer, 21(2):9-21, Febru- ary 1988.
Cluster Computing Project - Müller, Nolte (1998) (Correct)
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M. Dubios, C. Scheurich, and F. Briggs. Synchronization, coherence, and event ordering in multiprocessors. IEEE Computer, 21(2):9-21, February 1988.
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