L.C.V. dos Santos. Exploiting instruction-level parallelism: a constructive approach. PhD thesis, Eindhoven University of Technology, 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....with the advent of systems on a chip, system level behavioral modeling in high level languages is being used for initial system specification and analysis. All these factors have led to a renewed interest in high level synthesis from behavioral descriptions, both in the industry and in academia [1, 2, 3, 4, 5]. However, current synthesis efforts have several limitations: Synthesizability is guaranteed on a small, constrained sub set of the input language and the language level optimizations are few and their effects on final circuit area and speed are not well understood. Also, for designs with ....

.... when code motions only within basic blocks are enabled, the priority list scheduling heuristic we have presented reduces to the classical list scheduling approaches presented in previous 25 Number of Schedule Length Benchmark Basic Blocks Resources CVLS [13] HRA [37] Radivojevic [14] Santos [3] Spark kim [37] 7 2 ,1 ,2= 6 7 6 6 6 parker [38, 39] 20 2 ,3 ,5= 4 NA 4 4 4 waka [13] 9 1 ,1 ,2= 7 7 7 7 7 rotor [14] 11 2 ,2 ,1[ NA NA 8 8 8 Table 3. Comparison of schedule lengths with other methods using classical high level synthesis benchmarks. NA represents results that are not ....

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L.C.V. dos Santos. Exploiting instruction-level parallelism: a constructive approach. PhD thesis, Eindhoven University of Technology, 1998.

....source to source transformation phase and the scheduling phase. 1 Introduction Driven by the increasing size and complexity of digital designs, there has been a renewed interest in high level synthesis of digital circuits from behavioral descriptions both in the industry and in academia [1, 2, 3, 4, 5]. Recent years have seen the widespread acceptance and use of language level modeling of digital designs. A high level language such as a behavioral HDL (hardware description language) or C allows for additional freedom in the way a behavior is described compared to register transfer level (RTL) ....

L.C.V. dos Santos. Exploiting instruction-level parallelism: a constructive approach. PhD thesis, Eindhoven University of Technology, 1998.

....is called a guard [10] and to define Boolean expressions, which are called predicates. For instance, the execution condition of the operations enclosed by a basic block BB i is represented by a predicate G(BB i ) as illustrated in Figure 3a. Predicates can be efficiently obtained as explained in [12]. Let # i # c 1 , c 2 , ### , c n be the set of conditionals scheduled in a state s i (as pointed out by the arrows in the Figure 3b) During execution, a truth assignment to the conditionals in # i determines their Boolean valued outcome and is represented by a predicate. Every transition (s ....

....according to a given priority encoding #. The equivalence s n # # s m holds for a given #, iff all the following conditions hold: A n # A m and R n # R m , 1.1) # (A n ) # # j (A m ) # #, 1.2) #o z # # : # (o z ) # # j (o z ) 1. 3) A proof for this theorem can be found in [12]. 5. Implementation Algorithm 2 illustrates an efficient implementation. The pair (A n , R n ) is stored in a table for every scheduled state s n . For a given empty state s m about to be scheduled, condition 1.1 is checked via hashing. Only if a hit occurs, the other conditions are tested. ....

L.C.V. dos Santos, "Exploiting instruction--level parallelism : a constructive approach", PhD thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, Nov. 1998.

....F ) we assume that every node v 2 V is initially linked to exactly one node u 2 U . Each of such links is called an initial link. An initial link points to the initial position of an operation in the control flow prior to any code motion. A more elaborate initialization scheme is proposed in [13], where the links are established differently. For a given initialization, the effect of code motion is modeled as follows. Assume that an operation on is linked to some basic block BB j by means of link b . The motion of operation on from BB j to some basic block BB i is modeled by creating a ....

....state. Given a basic block BB i , the operations in A i may be available at distinct states, as a consequence of possibly different delays of their immediate data producers. The description of the effect of multicycle operations is not relevant for the analysis in this paper and can be found in [13]. V. EXPERIMENTAL RESULTS The techniques described in this paper are part of our constructive approach for exploiting ILP in HLS [13] They are implemented using the NEAT System, an object oriented framework for HLS. To support Boolean representation, we have used a BDD package. The described ....

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L.C.V. dos Santos, "Exploiting instruction-level parallelism: a constructive approach," PhD Thesis, Eindhoven University of Technology, 1998.

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