Ferri Abolhassan, Jorg Keller, and Wolfgang J. Paul. On the cost-effectiveness and realization of the theoretical PRAM model. Technical report, Universitat des Saarlandes, 1-6600 Saarbrucken, Germany, September 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... present in the switch; this puts a limitation on the switch cycle time, since the comparison cannot be done in parallel with sending the data off chip, as it can for Ultracomputer style combining (see Chapter 4) Implementations developed by a group at the University of Saar and described in [1, 42] use pipelining, simplified sorting hardware and overlapping networks to address some of these problems. An end to end synchronous method using combining in a Batcher double Omega network that is nonblocking for permutations was developed by Amano and Kalidou [7] In this circuit switched ....

Ferri Abolhassan, Jorg Keller, and Wolfgang J. Paul. On the cost-effectiveness and realization of the theoretical PRAM model. Technical report, Universitat des Saarlandes, 1-6600 Saarbrucken, Germany, September 1991.

....B ACM D.1.3; B.3.2 UDK 681.3.02 MemSim A Memory System Simulator for SDMMs Martti Forsell Report B 2000 1 1. Introduction Shared memory programming model on top of a physically distributed memory machine (SDMM) is a promising candidate for easy to program general purpose parallel computation [Schwartz80, Ranade87, Abolhas91, Leppnen94, Kautonen96, Forsell97]. There are, however, certain open technical problems which should be sufficiently solved before SDMM can meet the expectations. Among them is low level structure of the memory system. In most investigations [Leppnen94, Leppnen95, Forsell96, Kautonen96] it is assumed that memory modules are as ....

F. Abolhassan, J. Keller and W. J. Paul, On the Cost-effectiveness and Realization of the Theoretical PRAM Model, FB 14 Informatik, SFB-Report 09/1991, Universitt des Saarlandes, Saarbrucken, 1991.

.... switches [32] For probabilistic simulation, it is well known that by allowing packet combining, each step of a p processor PRAM can be simulated by a p node butterfly network in O#log p# time with high probability [46] Other deterministic and probabilistic simulation results are also reported in [1, 5, 18, 20, 22, 33, 34, 47, 48, 49]. A comprehensive survey can be found in [17] Recently, there have been significant advances in optical interconnections. Fiber optic communication technologies offer a combination of gigabit transmission capacity, predictable message delay, low interference and error probability. Based on the ....

F. Abolhassan, J. Keller, and W. Paul. On the cost-effectiveness and realization of the theoretical PRAM model. Technical Report 09/1991, FB Informatik, Universit at des Saarlandes, 1991.

.... most powerful PRAM variants, the CRCW model (see Gibbons and Rytter for full definitions [11] can be simulated probabilistically in this time [16] Much work has been done on such oblivious routing algorithms (see [24, 20, 5] Recent work has also focused on efficient hardware support (see [21, 1]) Routing supports the most difficult PRAM operations, those of reading and writing to shared memory, and thereby these results provide an upper bound to the cost of simulating a PRAM step. However, the real time required to simulate any particular step may be substantially less, since local ....

F. Abolhassan, J. Keller, and W.J. Paul. On the Cost-Effectiveness and Realization of the Theoretical PRAM Model. University of Saarlandes Research Report, Number 9/1991.

....this holds when the hardware requirements (implied by the algorithms) are taken into account. We also would like to know whether the combining queues method can be beaten The original stimulation to study coated meshes was to find alternatives to butterfly based work optimal PRAM constructions [2, 1, 18, 20]. In [16] such a construction for coated meshes was presented, although the constant factors left a lot to hope for. The advantage of coated butterflies over coated meshes is the asymptotically small diameter O(log N ) which allows the overloading factor also to be relatively small. However, the ....

....clockrate and or scalability. Coated meshes clearly do not have these layout related problems. On the other hand given sufficient parallel slackness, the coated meshes can be made to simulate PRAM models with relatively small cost. The cost (in terms of the number of routing steps) was made in [2, 1] smaller than 10 for coated butterflies using many techniques. Those techniques could also be applied to coated meshes to further improve efficiency (remember also Remarks 1.2 1.4) The interesting questions that remain are the size of the routing machinery, the hardware complexity of nodes and ....

F. Abolhassan, J. Keller, and W.J. Paul. On the Cost-Effectiveness and Realization of the Theoretical PRAM Model. Technical Report SFB Report 09/1991, Universitat des Saarlandes, W-6600, Saarbrucken, Germany, 1991.

....result is the same as if a single prefix operation were performed with the processors ordered by their index. McCOLL : GENERAL PURPOSE PARALLEL COMPUTING A parallel architecture which is very close in design to the Fluent machine is currently under construction at the University of Saarbr ucken [1, 2]. Valiant [258] has investigated the extent to which concurrent access to shared variables can be provided without the use of combining networks. Working with the BSP model, he has shown that if one has enough parallel slackness, then one can support concurrent accesses in software on networks ....

....to try to obtain the extreme case of the PRAM, where l and g are both 1. At any given point in time, the capabilities and economics of the technologies available will determine the most cost effective values of such parameters. An important advantage of the BSP model [258] over the PRAM [1, 2, 221] is that it provides an architecture independent framework which allows us to take full advantage of whichever values of l and g are the most cost effective at a given point in time. Large general purpose parallel computer systems will inevitably suffer hardware faults of various kinds during ....

F Abolhassan, J Keller, and W J Paul. On the cost-effectiveness and realization of the theoretical PRAM model. Research Report 09/1991, Fachbereich Informatik, Universit¨at des Saarlandes, Saarbr¨ucken, 1991.

....there have been only modest interest in actually implementing PRAM. The approach in the long running Ultracomputer project [23] is PRAM style, but the machine itself must still be regarded experimental 2 . A remarkable effort of implementation is being taken at the University of Saarbrucken [2, 1, 16]. The underlying interconnection network in that 128 processor machine is the butterfly. Other efforts to implement PRAMs also exist [38] This work was financially supported by the Academy of Finland. A preliminary version of this report was published in Proceedings of the Seventh Finnish ....

....for most of the CRCW PRAMs in two ways: by extending the routing machinery with on route combining mechanism [44] or by requiring that N = P 1 ffl for some ffl 0 [51] In [30] some of the above results were also given. An implementation of the ideas 5 of [44, 45, 51] is described in [2, 1, 16]. In addition to the above work optimal simulations, it is easy to construct others simply by taking some routing mechanism RN;P , which has P inputs and outputs, and can deliver N messages in time O(N=P ) from input to outputs (with high probability) 1.1.4 Some remarks What are we allowed to ....

F. Abolhassan, J. Keller, and W.J. Paul. On the Cost-Effectiveness and Realization of the Theoretical PRAM Model. Technical Report SFB Report 09/1991, Universitat des Saarlandes, W-6600, Saarbrucken, Germany, 1991.

....of the loose implementation (in the sense of Valiant s parallel slackness 3 ) of the PRAM models on meshes is the subject of [50] 1. 1 Previous work The authors are aware of only one implementation project that aims at the hardware implementation of PRAM style parallel computation [2, 1, 18]. This is a little bit alarming, since in the literature the PRAM model has been a very popular platform for the design of parallel algorithms. The underlying physical structure of that implementation is the butterfly interconnection structure. The PRAM approach is not all that strange although ....

.... optimal, because time cannot be smaller than the diameter, which is Omega Gamma 33 N ) Work optimal randomized simulations of PRAM models on low degree networks (butterfly, cube connected cycles, hypercubes) have been shown in [68] An implementation of the ideas of [56, 57, 68] is described in [2, 1, 18]. The deterministic simulation of PRAM models has also been investigated. Unfortunately, a fast deterministic simulation is not possible: If the shared memory is not small and several copies of each shared memory location are not maintained, then one cannot 3 Routing machinery and processors are ....

[Article contains additional citation context not shown here]

F. Abolhassan, J. Keller, and W.J. Paul. On the Cost-Effectiveness and Realization of the Theoretical PRAM Model. Technical Report SFB Report 09/1991, Universitat des Saarlandes, W-6600, Saarbrucken, Germany, 1991. 29 In [56] Ranade concludes the cost to be 12 log N .

....community as a vehicle for specifying and analyzing parallel algorithms in a comfortable way [12] Much effort has gone into asymptotically efficient simulations of PRAMs by networks of register machines. The least complicated one of these simulations is known as the fluent machine [25] In [2] it was shown that the fluent machine can be reengineered in such a way that it becomes surprisingly cost effective (if cost is measured in gate equivalents and time is measured in gate delays) The resulting design is called the SB PRAM. A prototype of this machine is presently under development ....

....surprisingly cost effective (if cost is measured in gate equivalents and time is measured in gate delays) The resulting design is called the SB PRAM. A prototype of this machine is presently under development at the university of Saarbrucken. Details about the physical design can be found in [2, 3, 13]. In the SB PRAM p = 128 processors with a BERKELEY RISC instruction set [21] are connected via a pipelined butterfly network to p memory modules. Addresses are hashed both to make the simultaneous access of all processors to different locations of the same memory module an unlikely event and to ....

Abolhassan, F., Keller, J., Paul, W.J.: On the Cost-- Effectiveness and Realization of the Theoretical PRAM Model., SFB 124 report, Universitat des Saarlandes, Saarbrucken (1991)

....section 4 we present an analysis of memory and time consumption. Section 5 gives a short discussion of the results of our work. 2. The SB PRAM The SB PRAM is a shared memory parallel computer which emulates the PRAM model from theoretical computer science [4] For implementation details consult [1, 2, 5, 7, 8, 11, 12]. 1 The programmers point of view of the SB PRAM is that of a priority CRCW PRAM [7] with n virtual processors (vP s) The priority CRCW model provides sequential semantics for the execution of parallel programs. The vP s are simulated by multithreaded physical processors (pP s) in round robin ....

F. Abolhassan, J. Keller, and W. J. Paul. On the Cost-- Effectiveness and Realization of the Theoretical PRAM Model. FB 14 Informatik, SFB-Report 09/1991, Universitat des Saarlandes, May 1991.

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F. Abolhassan, J. Keller and W. J. Paul, On the Cost-effectiveness and Realization of the Theoretical PRAM Model, FB 14 Informatik, SFB-Report 09/1991, Universitt des Saarlandes, Saarbrucken, 1991.

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F. Abolhassan, J. Keller and W. J. Paul, On the Cost-effectiveness and Realization of the Theoretical PRAM Model, FB 14 Informatik, SFB-Report 09/1991, Universitt des Saarlandes, Saarbrucken, 1991.

No context found.

F. Abolhassan, J. Keller and W. Paul. On the cost-effectiveness and realization of the theoretical PRAM model, technical report 09/91, FB Informatik, universitat des saarlandes. 1991.

No context found.

F. Abolhassan, J. Keller and W. Paul. On the cost-effectiveness and realization of the theoretical PRAM model, technical report 09/91, FB Informatik, universitat des saarlandes. 1991.

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