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P. Schneider and U. Schlichtmann, `Decomposition of Boolean Functions for Low Power Based on a New Power Estimation Technique', in Proc. 1994.

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This paper is cited in the following contexts:
Accurate Power Estimation Of Logic Structures.. - Theodoridis..   (Correct)

.... efficient low power design techniques have been developed to solve certain issues at all design levels [1] Also, a number of power estimation methods for combinational logic circuits have been developed [2] Recently, a number of probabilistic estimation methods, considering zero gate delay model [3,4,5] and real gate delay model [6,7] were proposed. The method presented in [5] is the most accurate assuming zero delay gate model since all types of correlations among the circuit signals are considered. The temporal correlation was captured by modelling the behaviour of a signal as a two state ....

P. Schneider and U. Schlichmann, "Decomposition of Boolean functions for low power based on a new power estimation technique," in Proc. of Int.Workshop on Low Power Design, pp. 123-128, NapaValley, CA, April 1994.


Design Technologies for Low Power VLSI - Pedram (1997)   (2 citations)  (Correct)

....efficient computational procedure for signal probability estimation. In [21] a procedure for propagating signal probabilities from the circuit inputs toward the circuit outputs using only pairwise correlations between circuit lines and ignoring higher order correlation terms is described. In [61] and [40] the temporal correlation between values of some signal x in two successive clock prob y ( prob x ( prob f x ( prob x ( prob f x ( cycles is modeled by a time homogeneous Markov chain which has two states 0 and 1 and four edges where each edge ij (i,j = 0, 1) is annotated with ....

P. Schneider and U. Schlichtmann. " Decomposition of boolean functions for low power based on a new power estimation technique. " In Proceedings of the 1994.


Probabilistic Modeling of Dependencies During.. - Marculescu.. (1998)   (1 citation)  (Correct)

....OF DEPENDENCIES 75 (a) b) Fig. 2. A lag one Markov chain describing temporal effects on line x: spatial correlations among probabilistic waveforms. Kapoor in [12] suggests an approximate technique to deal with structural dependencies, but on average the accuracy of the approach is modest. In [13], Schneider et al. rely on lag one Markov chains and account for temporal correlations; unfortunately, they assume independent transition probabilities among the primary inputs and use global OBDD s to evaluate switching activity (thus limiting the size of the circuits they can process) In what ....

....by building the global OBDD) This is visible in the topmost diagram in Fig. 7, where less than 20 of the nodes are estimated with a precision higher than 0.1. On the other hand, even if temporal correlations are taken into account, but the inputs are assumed to be spatially uncorrelated (as in [13]) only 80 of the nodes are estimated with an error less than 0.1 (middle diagram) Accounting for spatiotemporal correlations provides excellent results for highly correlated inputs; in the lowest diagram, 100 nodes are estimated with a precision better than or equal to 0.1 and for 90 of the ....

P. Schneider and U. Schlichtmann, "Decomposition of Boolean functions for low power based on a new power estimation technique," in Proc.


Method For Minimizing The Switching Activity Of Two-Level Logic.. - Soudris   (Correct)

....signal is in high logic level. Definition 2: The transition probability, E x i ( of a signal x i is defined as the probability a transition to occur either from logic value one to zero or from logic value zero to one, during two successive clock cycles. Adopting the power model proposed in [9], it is assumed that the primary inputs are mutually independent and each primary input is first order temporally dependent. Given a logic function, F f x f x x x n = 0 1 1 , the associated transition function ( Tf ) 9] is defined as: 5 ( Tf f x f x T = 0 (2) ....

....clock cycles. Adopting the power model proposed in [9] it is assumed that the primary inputs are mutually independent and each primary input is first order temporally dependent. Given a logic function, F f x f x x x n = 0 1 1 , the associated transition function ( Tf ) [9] is defined as: 5 ( Tf f x f x T = 0 (2) where ( f x 0 and ( f x T are the values of the function at the time instances t=0 and t=T, respectively. Studying (2) we infer that the transition function depends on the primary inputs and takes the value one, if and only if a ....

[Article contains additional citation context not shown here]

SCHNEIDER H. and SCHLICHTMANN U.: "Decomposition of Boolean Functions for Low Power Based on a New Power Estimation Technique", in Proc. of Int. Workshop on Low Power Design, Napa Valley, pp. 123-128, 1994. 17 # Inputs /Ratio Tot. Power (Area) Tot. Power (Power) Diff. (%)


A New Method For Low Power Design Of Two-Level Logic.. - Theodoridis..   (Correct)

....dynamic power dissipation consumed for charging and discharging the output load. A signal x i of the logic function, y f x f x x x n = 1 2 , can be described precisely with two attributes, namely the static probability, p x i ( and the transition probability, E x i ( [11, 12, 13]. More specifically, the static probability is defined as the percentage of the time in which the signal is high and, the transition probability is defined as the probability of the signal to make a transition during two successive clock cycles. Adopting the power model proposed in [13] it is ....

....( 11, 12, 13] More specifically, the static probability is defined as the percentage of the time in which the signal is high and, the transition probability is defined as the probability of the signal to make a transition during two successive clock cycles. Adopting the power model proposed in [13], it is assumed that the primary inputs are mutually independent and each primary input is first order temporally dependent. Given a logic function ( y f x f x x x n = 1 2 , the associated Transition function (Tf ) 13] is defined as: Tf f x f x T = 0 (3) where ( ....

[Article contains additional citation context not shown here]

H. Schneider and U. Schlichtmann, "Decomposition of Boolean Functions for Low Power Based on a New Power Estimation Technique", in Proc. of Int. Workshop on Low Power Design, Napa Valley, 1994, pp. 123-128.


A Probabilistic Power Estimation Method For.. - Theodoridis..   (Correct)

....as probabilistic methods and statistical ones. Moreover, considering the assumed gate delay model they are also characterized as zero and real gate delay methods. A survey of the power estimation methods for combinational logic circuits has been reported in [2, 3] Assuming zero gate delay model [4, 5] and real gate delay model [6,7,8,9] a number of probabilistic power estimation methods have been presented. In particular, a method for calculating the switching activity of the circuit nodes, using Order Binary Decision Diagrams (OBBDs) was proposed [4] Modeling the behavior of the logic ....

....[2, 3] Assuming zero gate delay model [4, 5] and real gate delay model [6,7,8,9] a number of probabilistic power estimation methods have been presented. In particular, a method for calculating the switching activity of the circuit nodes, using Order Binary Decision Diagrams (OBBDs) was proposed [4]. Modeling the behavior of the logic signal as an one step Markovian process the first order temporal correlation was captured. Moreover, structural correlation, which is coming from the reconvergent fanout nodes, was also considered by partitioning the circuit using techniques from the chip ....

P. Schneider and U. Schlichmann, "Decomposition of Boolean functions for low power based on a new power estimation technique," in Proc. of Int. Workshop on Low Power Design, pp. 123-128, Napa Valley, CA, April 1994.


Constrained Sequence Generation Using Stochastic.. - Marculescu.. (1996)   (Correct)

....is the ability to account for internal dependencies due to the reconvergent fan out in the circuit. This problem, which we will refer as the circuit problem , is by no means trivial. Indeed, a whole set of solutions have been proposed, ranging from approaches which build the global OBDDs [2][3] and therefore capture all internal dependencies, to efficient techniques which partially account for dependencies in an incremental manner [4] 7] Recently, some authors have pointed out the importance of correlations not only inside the target circuit, but also at the circuit inputs. If one ....

P. Schneider, U. Schlichtmann, and K. Antreich, `Decomposition of Boolean Functions for Low Power Based on a New Power Estimation Technique', in Proc. Intl. Workshop on Low Power Design, pp. 123-128, April 1994.


Power Analysis for Sequential Circuits at Logic Level - Schneider, Senn, Wurth (1996)   Self-citation (Schneider)   (Correct)

....and spatial correlations, we extend concepts which have successfully been used for transition probability analysis of combinational circuits. To cope with temporal correlations, Markov chains are applied. Markov chains have originally been proposed for estimation of combinational circuits in [14, 10, 13]. Spatial correlations of internal signals are captured based on reconvergence analysis. Reconvergence analysis has been used to analyse power in combinational circuits in [2, 13] Our technique combines the concepts of unrolling, Markov Chains, and reconvergence regions such that for a sequential ....

P. H. Schneider and U. Schlichtmann. Decomposition of Boolean Function for Low Power Based on a New Power Estimation Technique. In IEEE International Workshop on Low Power Design IWLPD, pages 123 -- 128, Apr. 1994.


Probabilistic Modeling of Dependencies During Switching.. - Radu Marculescu Diana (1998)   (1 citation)  (Correct)

No context found.

P. Schneider and U. Schlichtmann, `Decomposition of Boolean Functions for Low Power Based on a New Power Estimation Technique', in Proc. 1994.


Power Simulation and Estimation in VLSI Circuits - Pedram (1999)   (2 citations)  (Correct)

No context found.

P. Schneider and U. Schlichtmann, "Decomposition of Boolean Functions for Low Power Based on a New Power Estimation Technique," WLPD-94: International Workshop on Low Power Design, pp. 123-128, Napa, CA, April 1994.


Revision of Manuscript 42: - Gate-Level Power Estimation   (Correct)

No context found.

P. Schneider and U. Schlichtmann. Decomposition of boolean functions for low power based on a new power estimation technique. In Proceedings of 1994.


Power Estimation and Optimization at the Logic - Level Massoud Pedram   (Correct)

No context found.

P. Schneider and U. Schlichtmann. Decomposition of boolean functions for low power based on a new power estimation technique. In Proceedings of the 1994.


Probabilistic Modeling of Dependencies During.. - Marculescu.. (1998)   (1 citation)  (Correct)

No context found.

P. Schneider and U. Schlichtmann, `Decomposition of Boolean Functions for Low Power Based on a New Power Estimation Technique', in Proc. 1994.


Power Minimization in IC Design: Principles and Applications - Pedram (1996)   (72 citations)  (Correct)

No context found.

P. Schneider and U. Schlichtmann. " Decomposition of boolean functions for low power based on a new power estimation technique. " In Proceedings of the 1994.


Accurate And Fast Power Estimation Of Large.. - Theoharis.. (1999)   (Correct)

No context found.

P. Schneider and U. Schlichmann, "Decomposition of Boolean functions for low power based on a new power estimation technique," in Proc. of IWLPD, pp. 123-128, April 1994.

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