S. Unlu. Personal communication, February 1998. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Data Page Layouts for Relational Databases on Deep Memory.. - Ailamaki, DeWitt, Hill (2002) (1 citation) (Correct)
....redundancy when applying formulae to raw numbers, and ensured correctness by calculating each result in using multiple sets of correlated events. Finally, we stayed in contact with the processor vendors who helped decipher the counter values and approved the accuracy of our methodology [ 17] 21] [33]. Section 8.1 describes the additional software and hardware used in the third experimentation stage. The experiments for the first and second stages were conducted on a Dell 6400 PII Xeon MT system running Windows NT 4.0. This computer features a Pentium II Xeon processor at 400MHz, a 512 MB ....
Seckin Unlu and Andy Glew, Intel Corporation. Personal Communication, September-October 2000.
Summer 1999 Final Report Processor Performance of.. - Microsoft Corporation.. (Correct)
....platform. Section 3 describes the effects of varying several workload parameters such as access methods, selectivity, row size, and table size. Section 4 contrasts SQL Server and System B in terms of the effects instruction stream optimizations have on them; it also attempts a comparison of BBT [4] training scenario, investigating simpler alternatives that achieve much of the benefits seen with TPC C. 2 Execution time breakdown of three DBMSs This Section (a) corroborates previous results [1] on another platform, allowing them to be calibrated to the current study. b) gains insight ....
....about instruction demands on the memory hierarchy are exact. Data stalls are estimated, with a tendency to overestimate the second level cache data stalls (we multiply the number of misses by the measured memory latency, but there may be overlap with computation and or resource related stalls [4]) Resource stalls are measured. As discussed in Section 2.7, resource stalls can overlap with L2 data stalls (as estimated by our model) We use the difference between the measured CPI (clock cycles divided by the number of instructions retired) and the expected CPI (sum of measured or ....
Seckin Unlu. Intel Corporation. Personal communication, August 199s9.
DBMSs On A Modern Processor: Where Does Time Go? - Ailamaki, DeWitt, Hill, Wood (1999) (3 citations) (Correct)
....the number of occurrences for each event type (e.g. number of L1 instruction cache misses) during query execution. In addition, we can measure the actual stall time due to certain event types (after any overlaps) For the rest, we multiplied the number of occurrences by an estimated penalty [18][19] Table 4.2 shows a detailed list of stall time components and the way they were measured. Measurements of the memory subsystem strongly indicate that the workload is latency bound, rather than bandwidth bound (it rarely uses more than a third of the available memory bandwidth) In addition, ....
....shows a detailed list of stall time components and the way they were measured. Measurements of the memory subsystem strongly indicate that the workload is latency bound, rather than bandwidth bound (it rarely uses more than a third of the available memory bandwidth) In addition, past experience [18][19] with database applications has shown little queuing of requests in memory. Consequently, we expect the 1 Seckin Unlu and Andy Glew provided us with invaluable help in figuring out the correct formulae, and Kim Keeton shared with us the ones used in [10] results that use penalty ....
S. Unlu. Personal communication, September 1998.
DBMSs on modern processors: Where does time go? - Ailamaki, DeWitt, Hill, Wood (1999) (3 citations) (Correct)
....not able to measure T DTLB , because the event code is not available. For some of the events, we measured the actual stall time (after any overlaps) while for some others we measured the number of events that occurred during the query execution and then we multiplied by an estimated penalty [18][19] Measurements of the memory subsystem showed that the workload is latency bound, rather than bandwidth bound, because it rarely uses more than a third of the available memory bandwidth. Thus, the results that use penalty approximations are fairly accurate, because the 1 Seckin Unlu and Andy ....
S. Unlu. Personal communication, September 1998.
Performance Characterization of a Quad Pentium Pro .. - Keeton.. (1998) (68 citations) (Correct)
....the memory controller, falls behind in its internal processing. Since this phenomenon has been observed experimentally, but cannot be fully accounted for by the existing counters, we apply a 2X multiplier to the values measured by the counters to properly estimate memory system utilization [29]. As expected, memory system utilization decreases with increasing cache size, and increases with more processors. Utilization grows more slowly for the 1 MB cache size as the number of processors grows, reaching a maximum of nearly 40 for four processors. However, even at these relatively low ....
S. Unlu. Personal communication, February 1998.
Kimberly Keeton - David Patterson Yong (Correct)
No context found.
S. Unlu. Personal communication, February 1998.
Computer Architecture Support for Database Applications - Keeton (1999) (3 citations) (Correct)
No context found.
S. Unlu, Intel Corporation. Personal communication, February 1998.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC