| L. Barroso and K. Gharachorloo. "System design considerations for a commercial application environment," presented at the First Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW `98), in conjunction with the Fourth High Performance Computer Architecture Conference (HPCA-4), February 1998. |
.... 100 150 200 250 300 350 400 1234 Number of Processors Relative Throughput (percent) Linear 1 MB L2 512 KB L2 256 KB L2 Cache1P2P4P Linear 100 200 400 256 KB 100 194 345 512 KB 100 194 324 1 MB 100 184 296 52 have been shown to be a key factor in OLTP performance [12] [73] 83] This difficulty arises in some architectures because many RISC processors have been optimized to give the local CPU priority to the L2 cache. In addition, they are typically optimized for providing high bandwidth, rather than low latency, to the L2 cache for the CPU and incoming ....
L. Barroso and K. Gharachorloo. "System design considerations for a commercial application environment," presented at the First Workshop on Computer Architecture Evaluation using Com- mercial Workloads (CAECW `98), in conjunction with HPCA-4, February 1998.
....provide a more structured environment for system level simulation research in general. A more recent tool, SimOS, models a MIPS based multiprocessor (Rosenblum et al. 1995 and 1997, Witchel et al. 1996) SimOS can boot and run Irix. Newer versions of SimOS model other processors, such as the Alpha (Barroso et al. 1998). Both SimOS and SimICS have pursued similar goals and have thus, inevitably, arrived at similar solutions on many issues. For instance, both tools allow adding enduser memory hierarchy models, support copy on write disk images, can run off a local network as a virtual workstation, and provide ....
Barroso, L. A. and K. Gharachorloo. 1998. System Design Considerations for a Commercial Application Environment First Workshop on Computer Architecture Evaluation Using Commercial Workloads. In conjunction with the Fourth International Symposium on High Performance Computer Architecture (HPCA-4), Las Vegas, Sunday Feb. 1, 1998.
....recent studies began the examination of the architectural impacts of transaction processing database workloads for symmetric multiprocessors. Most of the studies have focused on some variation of the now defunct DebitCredit benchmark, also known in various incarnations as TP1, TPC A, and TPC B [1] [5] 16] 22] 25] 27] This benchmark has been withdrawn by the Transaction Processing Council. A few have examined the more complex TPC C order entry workload [6] 16] Only two of these papers have explored the effectiveness of out oforder execution for the TPC B workload [1] 25] None ....
....and TPC B [1] 5] 16] 22] 25] 27] This benchmark has been withdrawn by the Transaction Processing Council. A few have examined the more complex TPC C order entry workload [6] 16] Only two of these papers have explored the effectiveness of out oforder execution for the TPC B workload [1] [25] None examine the effectiveness of out of order processors for TPC C. In general, we observe that these papers corroborate our findings, with a few exceptions. Because the scope of the studies is vast, we defer the discussion of similarities between our work and these related studies until ....
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L. Barroso and K. Gharachorloo. "System design considerations for a commercial application environment," presented at the First Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW `98), in conjunction with the Fourth High Performance Computer Architecture Conference (HPCA-4), February 1998.
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L. Barroso and K. Gharachorloo. "System design considerations for a commercial application environment," presented at the First Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW `98), in conjunction with the Fourth High Performance Computer Architecture Conference (HPCA-4), February 1998.
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