A. Abnous and J. M. Rabaey. Ultra-low-power domain-specific multimedia processors. presented at Proc. IEEE VLSI Signal Processing Workshop  Home/Search   Document Not in Database   Summary   Related Articles   Check

....which the device will operate. With this knowledge, designers could then remove from the reconfigurable array hardware and programming points that are not needed and would otherwise reduce system performance and increase the design area. Architectures such as RaPiD [4] PipeRench [6] and Pleiades [1], have followed this design methodology in the digital signal processor (DSP) computational domain, and have shown improvements over reconfigurable processors within this space. This ability to utilize custom arrays instead of ASICs in high performance sac designs will provide the post fabrication ....

Abnous, A. and Rabaey, J. M. "Ultra-low-power domainspecific multimedia processors," Proc. of lEEE VLSI Signal Processing Workshop, Oct. 1996.

....a connection centric system an interesting combination is to use clocks local to individual logic modules for synchronous operation in each module, and an asynchronous protocol between functional modules for asynchronous communication in the interconnection network. Recently several studies (e.g. [2][25] indicate that it would be worthwhile to consider such an approach to eliminate the necessity of distributing a global clock between block of larger granularity. In this way, the interface circuitry would represent a very small overhead component, and the most energy consuming aspects of ....

Abnous A., Rabaey J.: "Ultra-low-power domain-specific multimedia processors", VLSI Signal processing IX, ed. W. Burleson et al., IEEE Press, pp. 459-468, November 1996.

....been made that energy in real life systems is to a large extend dissipated in communication channels, sometimes even more than in the computational elements. Experiments have demonstrated that in designs, about 10 to 40 of the total power may be dissipated in buses, multiplexers and drivers [1]. This amount can increase dramatically for systems with multiple chips due to large off chip bus capacitance. The power consumption of the communication channels is highly dependent on algorithm and architecture level design decisions. Two properties of algorithms and architectures are important ....

....a long distance is to integrate a processor in the memory, as for example proposed by Patterson in intelligent RAM [53] 48] This approach also reduces the processor memory bottleneck. At system level locality can be applied by dividing the functionality of the system into dedicated modules [1][44] When the system is decomposed into application specific modules, the data traffic can be reduced, because unnecessary data copies are removed. For example, in a system where a stream of video data is to be displayed on a screen, the data can be copied directly to the screen memory, without ....

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Abnous A., Rabaey J.: "Ultra-low-power domain-specific multimedia processors", VLSI Signal processing IX, ed. W. Burleson et al., IEEE Press, pp. 459-468, November 1996.

....By generating a custom reconfigurable array for a computation domain, we can reduce the amount of useless hardware and programming points that would otherwise occupy valuable area or slow the computations. Architectures such as RaPiD [Ebeling96] PipeRench [Goldstein99] and Pleiades [Abnous96] have made progress in this direction by targeting multimedia and DSP domains. The RaPiD group has also proposed the synthesizing of custom RaPiD arrays for different application sets [Ebeling98, Cronquist99b] In many ways this effort can be viewed as a first step in this direction. We are ....

A. Abnous, J. Rabaey, "Ultra-Low-Power Domain-Specific Multimedia Processors", Proceedings of the IEEE VLSI Signal Processing Workshop, October 1996.

....which the device will operate. With this knowledge, designers could then remove from the reconfigurable array hardware and programming points that are not needed and would otherwise reduce system performance and increase the design area. Architectures such as RaPiD [2] PipeRench [3] and Pleiades [4], have followed this design methodology in the digital signal processor (DSP) computational domain, and have shown improvements over reconfigurable processors within this space. This ability to utilize custom arrays instead of ASICs in high performance SOC designs will provide the post fabrication ....

.... ( Select[3] Select[2] Select[1] Select[0] assign Out bus[1] In ( Select[3] Select[2] Select[1] Select[0] assign Out bus[2] In ( Select[3] Select[2] Select[1] Select[0] assign Out bus[3] In ( Select[3] Select[2] Select[1] Select[0] assign Out bus[4] = In ( Select[3] Select[2] Select[1] Select[0] assign Out bus[5] In ( Select[3] Select[2] Select[1] Select[0] assign Out bus[6] In ( Select[3] Select[2] Select[1] Select[0] assign Out bus[7] In ( Select[3] Select[2] Select[1] Select[0] assign ....

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A. Abnous and J. M. Rabaey, "Ultra-low-power domain-specific multimedia processors," Proc. of IEEE VLSI Signal Processing Workshop, Oct. 1996.

....as variable hardware resource availability. Also inspirational to SCORE are heterogeneous systems that use streaming data flow to tie together arbitrary processors (conventional, special purpose, and or reconfigurable) Examples include MIT s Cheops [5] MagicEight [23] and Berkeley s Pleiades [1]. These systems provide interesting performance point with a mix of processing elements. Our work on SCORE for hybrid reconfigurable hardware (Section 4) builds on these models by defining a common programming model for all processing elements (microprocessor and reconfigurable in our case) and by ....

Arthur Abnous and Jan Rabaey. Ultra-low-power domain-specific multimedia processors. In Proceedings of the IEEE VLSI Signal Processing Workshop (VSP'96), October 1996.

....in the inset in Figure 1, each PE is equipped with a local controller, local memory, a router, and a computational node. Communication and buffering are logic in the figure, yet it is obvious that both must be as local as possible. The PEs may be satellites to the Global controller, as e.g. in [1] or they may be connected to a 1D or 2D switch network as in [8] Now, the problem is to determine values for the template s parameters , i.e. to derive one or more specific processors Jacobi processors which is or are satisfying the performance cost ratio requirements. To derive the Jacobi ....

A. Abnous and J. Rabaey. Ultra-low-power domain-specific multimedia processors. In VLSI Signal Processing, IX, pages 461--470, 1996.

....TERMINAL: A PORTABLE DEVICE FOR WIRELESS INFORMATION ACCESS 1085 signal strength (0. 25 Watts) This accounts for 30 percent of the total power dissipation, and the desire to substantially reduce the power dissipation in this subsystem has fueled research both in low power reconfigurable logic [12], and in low power RF transceiver design [9] In [9] a fully integrated, combined RF and baseband CDMA receiver implemented in 0.6 micron CMOS, was described, and the total power consumption was less than 30 milliwatts. It is believed that for an indoor pico cellular environment, where the ....

# A. Abnous and J. Rabey, "Ultra-Low-Power Domain-Specific Multimedia Processors," Proc. IEEE VLSI Signal Processing Workshop, San Francisco, Oct. 1996.

....via some kind of programmable interconnect (See Figure 1) These architectures are devised to be used in real time, high performance signal processing applications. Examples of these new architectures are the Prophid architecture [12] The Jacobiumarchitecture [15] and the Pleiades architecture [1], to be used in respectively, video consumer appliances, adaptive radar processing,and mobile communicationdevices. Thesearchitectures have in common that they exploit parallelism using instruction level parallelism offered by the microprocessor and coarse grained parallelism offered by the ....

A. Abnous and J. Rabaey. Ultra-low-power domain-specific multimedia processors. In VLSI Signal Processing, IX, pages 461--470, 1996.

....is due to the overhead in interconnection structure and due to the control activity of a processor. On the other hand, processors are much more flexible and can be used to implement any softwareprogrammable task. Thus, there is a trade off between flexibility and low power consumption (ref. to [3] for details) ASIP implementation in hardware in the current project is achieved using HDLbased logic synthesis and semi custom ASIC design to get the best time to market. The abstraction level of semi custom design enables the designer to cope with complex systems like DVB T and thus helps to ....

Arthur Abnous and Jan Rabaey, Ultra-Low-Power Domain-Specific Multimedia Processors, Proc. IEEE VLSI Sig. Proc. Workshop, San Francisco, California, USA, October 1996.

....task. This is due to the flexible interconnection structure and the control overhead of a processor. On the other hand, processors are much more flexible and can be used to implement any software programmable task. Thus, there is a trade off between flexibility and low power consumption (ref. to [3] for details) ASIP implementation in hardware in the current project is achieved using HDL based logic synthesis and semi custom ASIC design to get the best time to market. Synthesized logic has an overhead in area and power consumption with respect to full custom design. In [8] a comparison ....

Arthur Abnous and Jan Rabaey, Ultra-Low-Power Domain-Specific Multimedia Processors, Proc. IEEE VLSI Sig. Proc. Workshop, San Francisco, California, USA, October 1996.

.... resources [8] Srivastava, et al. performed a demand driven operation and predictive powerdown to avoid wasteful transitions [9] Abnous and Rabaey proposed a hybrid architecture exploiting application specific units that consume less power than general purpose ones to support programmability [10]. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between consecutive inputs to an execution unit so that the switched capacitance of the execution unit is reduced. The proposed method uses DBT(Dual Bit Type) model [11] for estimating power ....

A. Abnous and J. M. Rabaey, "Ultra-low-power domain-specific multimedia processors," in Proc. of IEEE VLSI Signal Processing Workshop, Oct. 1996.

....IDF graph containing dynamic operators. SCORE shares a gross similarity to heterogeneous systems which use streaming data flow to tie together arbitrary processors (conventional, special purpose, and or reconfigurable) including MIT s Cheops [4] MagicEight [35] 34] and Berkeley s Pleiades [26] [1]. The programming model of these systems is more restricted than SCORE, typically based on a pre defined set of streaming operations. Furthermore, SCORE provides a stronger abstract model allowing pages (processors) to be swapped as 3 needed and hiding implementation limitations like buffer ....

Arthur Abnous and Jan Rabaey. Ultra-Low-Power Domain-Specific Multimedia Processors. In Proceedings of the IEEE VLSI Signal Processing Workshop (VSP'96), October 1996.

....processors were able to compute with greater e#ciency than software alone, having less software overhead due to address generation, branching, and function calls and exploiting more parallelism than is possible with the processor s normal data path. One hybrid processor RL system called Pleiades [9, 10] has specifically targeted ultra low power, embedded digital signal processing. The approach fuses an ARM core with a combination of reconfigurable logic, reconfigurable data path, and or reconfigurable data flow resources. In this case, due to power and performance constraints, the RISC core is ....

Arthur Abnous and Jan Rabaey. Ultra-low-power domain-specific multimedia processors. In Proceedings of the IEEE VLSI Signal Processing Workshop. IEEE, IEEE, October 1996.

....in the inset in Figure 1, each PE is equipped with a local controller, local memory, a router, and a computational node. Communication and bu#ering are logic in the figure, yet it is obvious that both must be as local as possible. The PEs may be satellites to the Global controller, as e.g. in [1] or they may be connected to a 1D or 2D STW SAFE99 Application and Architecture Modeling for Parallel Execution of Jacobi type Algorithms 377 switch network as in [12] Now, the problem is to determine values for the template s parameters , i.e. to derive one or more specific processors Jacobi ....

Arthur Abnous and Jan Rabaey. Ultra-Low-Power Domain-Specific Multimedia Processors, volume ASSP-39, chapter 9, pages 461--470. IEEE Signal Processing Society, ieee operations center p.o. box 1331 445 hoes lane piscataway, nj 08855-1331 usa edition, 1996.

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A. Abnous and J. M. Rabaey. Ultra-low-power domain-specific multimedia processors. presented at Proc. IEEE VLSI Signal Processing Workshop

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A. Abnous and J. Rabaey, "Ultra-Low-Power Domain-Specific Multimedia Processors," Proceedings of the 1996.

....whose design involves trading off the flexibility of a general purpose programmable device to achieve higher levels of energy efficiency, while maintaining the flexibility to handle a variety of algorithms within the domain of interest. The Berkeley Pleiades architecture is based on this approach [1]. In this paper we analyze the energyefficiency of the Pleiades architecture, and we compare it to other programmable architectures. 2 Architectural Evaluation For the purposes of this study,we chosea set of programmable architectures ranging from generalpurpose microprocessors to ....

A. Abnous and J. Rabaey, "Ultra-Low-Power Domain-Specific Multimedia Processors," Proceedings of the IEEE VLSI Signal Processing Workshop,San Francisco, October 1996.

No context found.

A. Abnous and J. M. Rabaey, "Ultra-low-power domain-specific multimedia processors," in Proc. IEEE VLSI Signal Processing Workshop, Oct. 1996, pp. 461--470.

No context found.

A. Abnous and J. Rabaey, "Ultra-low-power domain-specific multimedia processors," in Proc. VLSI Signal Process. IX, Oct. 1996.

No context found.

A. Abnous and J. Rabaey, "Ultra-low-power domain-specific multimedia processors, " in Proc. VLSI Signal Processing IX, Oct. 1996.

No context found.

A. Abnous and J. M. Rabaey, "Ultra-low-power domain-specific multimedia processors," in Proc. IEEE VLSI Signal Processing Workshop, Oct. 1996, pp. 461--470.

No context found.

A. Abnous and J. Rabaey, "Ultra-low-power domain-specific multimedia processors," in Proc. VLSI Signal Process. IX, Oct. 1996.

No context found.

A. Abnous and J. Rabaey, "Ultra-low-power domain-specific multimedia processors, " in Proc. VLSI Signal Processing IX, Oct. 1996.

No context found.

Abnous A, Rabaey J.: "Ultra-Low-Power Domain-Specific Multimedia Processors," Proceedings of the IEEE VLSI Signal Processing Workshop, San Francisco, October 1996.

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