S. Note, W. Geurts, F. Catthoor, and H. D. Man. Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications. In Proc. of the 28th Design Automation Conference, pages 597--602, June 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of the buffered interconnects that carry operands among function units. This paper describes techniques that greatly reduce buffering and interconnect costs by tailoring interconnects to specific application needs. Operand transport mechanisms have been developed for a varietyofcustom solvers [2, 3, 7]. However, unlike prior work, this paper focuses on transport mechanisms for software pipelined loops. This problem can be approached from one of two extreme viewpoints. A fully centralized view places all virtual registers in a common shared file. This maximizes the potential that multiple ....

....such ShiftQs may also be specialized in bitwidth as each register element within the ShiftQ needs to be only as wide as the widest operand that it must support. Another typical approach for designing fully customized datapaths is to assign a separate storage structure to each EVR in the program [2, 7] as shown in Figure 3. When operands are of uniform width, this approach increases overall cost as it precludes the sharing of register storage elements among multiple EVRs. However, when operands have differing bitwidth, the storage of these operands in separate ShiftQs allows each shiftQ to be ....

S. Note, W. Guerts, F. Catthoor, and H. D. Man. Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications. In Proceedings

....that for many digital signal processing applications low order bits are often not needed and can be discarded in order to reduce hardware cost without introducing undue error into the application. Automatic datapath synthesis and has a long history and vast literature. For example, Cathedral III [17], represents a complete synthesis system developed at IMEC and illustrates 36 one approach to high level synthesis. It uses an applicative language for program specification and designs customized datapaths for DSP applications from this specification. Our work focuses specifically on datapath ....

S. Note, W. Geurts, F. Catthoor, and H. D. Man, "Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications," in Proceedings of the 28th ACM/IEEE Design Automation Conference,pp.597--602, June 1991.

....has been based on the synchronous data flow model of computation. As pointed out earlier, most high level synthesis systems for DSP, video, and other numerically intensive applications either assume that all input and delay node samples are available at the same time (all phases are zero) 33] [34], 40] or indirectly assign values to the phases by using schedulers that incorporate techniques such as overlapped scheduling and software pipelining to generate complex time shapes [12] 25] 38] However, only recently has some limited work been done on relaxing the assumption that all ....

S. Note, W. Geurts, F. Catthoor, and H. De Man, "`Cathedral-III' architecture-driven high level synthesis for high throughput DSP applications, " in Proc. Design Automation Conf., 1991, pp. 597--602.

.... descriptions to hardware libraries or instruction sets which involves template matching and selection, and clock selection [Cor96] The IMEC high level synthesis group was one of the first to attempt template matching by addressing the issues of application specific functional units using ILP [Geu92, Not91]. Rao and Kurdahi proposed the use of template matching within a framework of regularity extraction for addressing partitioning [Rao92] 4. GLOBAL FLOW: IPP FOR BEHAVIORAL SYNTHESIS The generic approach for protecting solutions to the above problems is shown in Figure 1. Watermarking of the ....

S. Note, W. Geurts, F. Catthoor, and H. De Man. Cathedral-III: architecture-driven high-level synthesis for high throughput DSP applications. Design Automation Conference, pp.597--602, 1991.

....the given applications. It is important to come up with a platform, which meets most of the demands of all applications. The idea of having dedicated data path according to the demand of a specific application is not a new methodology. This paradigm has been studied in DSP architecture design in [8, 9]. An architecturedriven high level synthesis of DSP applications, called Cathedral III, is presented. Similar to SPS project, the application specific units are extracted and synthesized from data flow graph of the given application instead of selecting dedicated data paths from predefined ....

T. Note, W. Geurts, F. Catthoor, and H. De Man, "Cathedral-III : Architecture-Driven High-level Synthesis for High Throughput DSP Applications", Proc. of 28th ACM/IEEE Design Automation Conference, 1991.

....originally proposed for VLIW architectures and the goal there was instruction scheduling [20] 10 2.2 Related Work on Global Optimizations Global optimization is a challenging task and some synthesis frameworks in the past have addressed the issue. Among related work, the Cathedral III system [46] enables global resource sharing by clustering computations corresponding to loops and function calls. However, the emphasis in Cathedral III is on producing the clusters optimally and then scheduling the entire application on the clusters. In our framework, we construct the clusters in a greedy ....

S. Note, W. Geurts, F. Catthoor and H. D. Man, Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications, 28th DAC, 1991.

....of uniformity of operators (Section 4.1.1) Therefore, this section will concentrate on the introduction and description of the regularity property measure. 4.3. 1 Regularity The influence of regularity on physical layout characteristics has been observed by several high level synthesis groups [Not91, Rao92]. Regularity has only been treated qualitatively until now, and the exploration of its potential is in an early phase.We define regularity using the following simple formula: 8) The size component is the number of operations and data transfers executed in the computation. The descriptive ....

S. Note, W. Geurts, F. Catthoor, H. De Man, "Cathedral-III: Architecture-Driven High-Level Synthesis for High Throughput DSP Applications," Proc. 28th DAC, pp. 597-602, 1991.

.... tree matching method has been used in a number of successful compiler projects [Aho90] Through use of the tree processing language Twig [Aho89] it was also applied in logic synthesis for technology mapping [Keu87] Template matching has attracted a great deal of interest in behavioral synthesis [Not91]. Other pattern matching approaches in logic synthesis were predating the application of tree matching methods [Dar81, DeG85] Data watermarking embeds hidden data into an object for the purpose of identification, annotation, and copyright. Two main directions in watermarking have emerged. The ....

S. Note, W. Geurts, F. Catthoor, H. De Man: "Cathedral-III: Architecture-Driven High Level Synthesis for High Throughput DSP Applications", ACM/IEEE DAC'91, pp. 597-602, 1991.

....these implementations are mostly constrained to a special application and therefore not very flexible. The documentation of their algorithmic behavior is not mostly purely textual which obstructs the re use of these sophisticated designs even further. General purpose high level design environments [16, 17, 18] synthesize circuits from a behavioral description which hides implementation details allowing the system designer to focus on behavioral issues. One drawback of this approach is that existing dedicated IP can not be easily re used. The design environment ComBox [19] for high throughput data flow ....

S. Note, W. Geurts, F. Catthoor, and H. De Man, "Cathedral-III: Architecture-Driven high-level synthesis for high throughput DSP applications," in Proc. of the 28th ACM/IEEE Design Automation Conference, pp. 597--602, 1991.

....an explicit notion of such an architecture template. Furthermore, ASPPs have clear functions, e.g. filters, whereas in our case the processing elements can have any input output relation. In the Cathedral III environment, partitioning of applications in the synthesis of data paths is addressed [9, 20]. The used approach is very similar to the approach we present in this paper, but it is focused on single applications, whereas we focus on a set of applications. Clustering, or partitioning, that we use for our analysis, is a technique that is widely used. It is used in floorplan design, to ....

Stefaan Note, Werner Geurts, Francky Catthoor, and Hugo De Man. Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications. In Proc. 28th DAC, pages 597--602, June 1991.

.... descriptions to hardware libraries or instruction sets which involves template matching and selection, and clock selection [Cor96] The IMEC high level synthesis group was one of the first to attempt template matching by addressing the issues of application specific functional units using ILP [Geu92, Not91]. Rao and Kurdahi proposed the use of template matching within a framework of regularity extraction for addressing partitioning [Rao92] 4. GLOBAL FLOW: IPP FOR BEHAVIORAL SYNTHESIS The generic approach for protecting solutions to the above problems is shown in Figure 1. Watermarking of the ....

S. Note, W. Geurts, F. Catthoor, and H. De Man. Cathedral-III: architecture-driven high-level synthesis for high throughput DSP applications. Design Automation Conference, pp.597--602, 1991.

....uniformly and incorporated in to the timing analysis. We illustrate these ideas using the dashboard controller [1] as an example. 1. 3 Related Earlier Work There has been a lot of excellent earlier work on modeling communications systems [6, 21, 23, 11] There are several tools, like MISTREL [22], PTOLEMY [19] PHIDEO [24] PROPHID [15, 16] that include communication specification and sharing of channels among various tasks. However, most of these tools do not address the problem at the level of abstraction that we do in this paper. Also, some of these tools, like PROPHID and PHIDEO are ....

S.Note, W.Geurts, F.Catthoor, and H.De Man. Cathedral iii: Architecture driven high-level synthesis for high throughput dsp applications. In Proc. Design Automation Conference, San Francisco, pages 597--602, June 1991.

....design of highthroughput ASIC circuits to be fabricated in deep submicron CMOS technology and therefore aims the minimum impact of interconnections on chip performance. In order to cope with the high throughput requirements, the method is dedicated to a lowly multiplexed architectural design style[18]. The key part of this architecture is Application Specific Data path Units (ASUs) each of which can execute a group of operations in one clock cycle. Since the delays of inter connections between the ASUs are much longer than the delays of intra connections, functional identification of these ....

S.Note, et al., "Cathedral-III: Architecture-Driven HighLevel Synthesis for High Throughput DSP Application", Proc. 28th DAC, pp.597-602, 1991.

No context found.

S. Note, W. Geurts, F. Catthoor, and H. De Man, "Cathedral III: Architecture driven high-level synthesis for high throughput DSP applications," in Proc. 28th ACM/IEEE Design Automat. Conf., DAC'91, San Francisco, CA, June 1991, pp. 597--602.

....to exploit factorisation and common subexpression opportunities amongst all Address Expressions (AEs) before the architecture mapping. Additionally, specific synthesis techniques aiming at the timeshared cluster level (based on our Cathedral 3 methodology for lowly multiplexed data path synthesis [13], 14] can be used to trade off more efficiently cycle, area and or power during the architecture exploration step, instead of going down directly to more traditional operation level scheduling and allocation. These system level opportunities are not fully exploited by more conventional HW ....

....from the global master cMMU controller. In the cACU case, the AEs are realized as ApplicationSpecific Units (ASUs) with custom arithmetic building blocks selected from a library. Use is made here by us of a subset of the Cathedral 3 methodology for lowly multiplexed custom data path synthesis [13]. This architecture style has been first proposed in our environment as an alternative to the iAGU style for the synthesis of address generators [10] 11] However, it is also being incorporated in more recent design flows proposed in academia [20] For cACUs, the complete set of iterator states ....

[Article contains additional citation context not shown here]

S.Note, W.Geurts, F.Catthoor, H.De Man, Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications, Proc. 28th ACM/IEEE Design Automation Conf., pp. 597-602, 1991.

.... is followed by target architecture selection, loop invariant code hoisting (CH) induction variable analysis (IVA) and algebraic transformations (AT) The resulting AEs are then mapped onto the custom hardware processor by using specific synthesis techniques aimed at the time shared clusterlevel [14]. However, this ADOPT methodology does limited CH and IVA and considers these two steps isolated from each other. In this paper, we refine the ADOPT script (see Figure 1) to propose a more detailed analysis of the interaction between the global scope CH and IVA stages and incorporate operation ....

S.Note, W.Geurts, F.Catthoor, H.De Man, Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications, Design Automation Conference, 1991.

.... is followed by target architecture selection, loop invariant code hoisting (CH) induction variable analysis (IVA) and algebraic transformations (AT) The resulting AEs are then mapped onto the custom hardware processor by using specific synthesis techniques aimed at the time shared cluster level [14]. However, this ADOPT methodology does limited CH and IVA and considers these two steps isolated from each other. In this paper, we refine the ADOPT script (see Figure 1) to propose a more detailed analysis of the interaction between the global scope CH and IVA stages and incorporate operation ....

S.Note, W.Geurts, F.Catthoor, H.De Man, Cathedral-III: Architecture driven high-level synthesis for high throughput DSP applications, Design Automation Conference, 1991.

....the fixed rate assumption does not hold and more flexibility is needed. For this purpose, our work has concentrated on the following issues. The accelerator algorithm is defined by means of a signal flow graph (SFG) The accelerator datapath is defined as a set of application specific units (ASU) [6]. An ASU is a bit parallel hardware operator, able to execute one or more micro instructions. The micro instructions are defined by subsets or clusters of the SFG. Each cluster corresponds to one micro instruction, and the set of all clusters covers the complete SFG. This way, the accelerator ....

S. Note, W. Geurts, F. Catthoor, H. De Man, "Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications", Proc. DAC91, San Francisco, Calif., pp. 597-- 602, 1991.

No context found.

S. Note, W. Geurts, F. Catthoor, and H. D. Man. Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications. In Proc. of the 28th Design Automation Conference, pages 597--602, June 1991.

No context found.

S. Note, W. Geurts, F. Catthoor, and H. De Man, "Cathedral-III: architecturedriven high-level synthesis for high throughput DSP applications," ACM/IEEE 28th Design Automation Conference, pp. 597-602, 1991.

No context found.

S. Note, W. Geurts, F. Catthoor, and H. D. Man. Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications. In Proc. of the 28th Design Automation Conference, pages 597--602, June 1991.

No context found.

S. Note, W. Geurts, F. Catthoor, and H. D. Man. Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications. In Proc. of the 28th Design Automation Conference, pages 597--602, June 1991.

No context found.

S. Note, W. Geurts, F. Catthoor, H. De Man, "Cathedral-III: Architecture-Driven Highlevel Synthesis for High Throughput DSP Applications", 28th ACM/IEEE Design Automation Conference, 1991.

No context found.

S. Note, et al. Cathedral III: Architecture driven high-level synthesis for high throughput DSP applications. In Proceedings of the 28th ACM/IEEE Design Automation Conference, DAC 91, San Francisco, CA, 1991, pp. 597 -- 602.

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S.Note, W.Geurts, F.Catthoor, and Man, H. "Cathedral-III: Architecture Driven High-Level Synthesis for High Throughput DSP Applications". Proc. 28th ACM/IEEE Design Automation Conf (1991), 597-602.

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