F. Najm, "Transition Density: A New Measure of Activity in Digital Circuits," IEEE Transactions on CAD, Vol. 12, No. 4, pp. 310-323, 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....supply voltage or current waveforms or both. These are too slow to handle very large circuits. In a probabilistic technique [5, 6, 7] user supplied input signal probabilities are propagated into the circuit. Various approaches based on different probabilistic measures such as transition density [8] are proposed. In a statistical technique [9, 10] the circuit is simulated with randomly generated input vectors until power converges to the average power where convergence is tested by statistical mean estimation techniques. At the architectural level, Landman et al. [11] pre VHDL Simulator ....

F. N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Transanctions on CAD, vol. 12, no. 2, pp. 310-323, February 1993.

....are used. Delay constraint are either neglected[3] or roughly estimated[9] 12] In this paper, we present a delay constrained power optimization algorithm based on the notion of generalized implication supergate rewiring[2] This type of rewiring has the property that the transition densities [8] at the roots of the supergates remain unchanged when wires are reconnected. This enables us to design a global optimization algorithm tightly coupled with traditional discrete gate sizing for a careful and accurate power delay trade off exploration. 2. Preliminaries The average power ....

....to use the estimation as a P av P load P short P leak = P leak leak sub routine inside our algorithm, we choose to neglect the effect of glitching and use a zero delay model instead. Najm has introduced the notion of equilibrium probability and transition density for power estimation[8]. The equilibrium probability of a signal x, denoted P(x) is the fraction of time x is evaluated to logic 1. The transition density of x, denoted D(x) is the average number of transitions per unit time. Under spatial and temporal independence assumption, an efficient algorithm was introduced to ....

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F. N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, Feb, 1993, pp. 310-323

.... activity (see, for example, 2] 7] This is motivated by the fact that the average power dissipation for a CMOS logic gate can be approximated by Pave = 2 CLV dd f , where CL is the load capacitance, Vdd is the supply voltage and f is the frequency of one to zero or zero to one transitions [1, 8]. Under this model, the average power dissipation is proportional to the average Hamming distance (i.e. the number of places at which encodings of consecutive states differ, averaged over the frequencies with which pairs of consecutive states appear during the operation of the system) This ....

F. N. Najm, "Transition density: a new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 310--323, Feb. 1993.

....switching power dissipation model we use is given below. I . V 2 Pis = Ci TDi (10) where Pis is the average switching power dissipation, V is power supply voltage, Ci is the output capacitance, and TDi is the transition density, all corresponding to gate ri. The transition density is defined [11] as limT n(T) T, where n(T) represents the number of transitions the gate performs in time T. The use of transition density allows a gate with lower switching probabilities to be sized larger. The short circuit power is known to be dependent on the input transition time to a great extent, and ....

F. N. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 310-323, Feb. 1993.

.... efficient low power design techniques have been developed to solve certain issues at all design levels [1] Also, a number of power estimation methods for combinational logic circuits have been developed [2] Recently, a number of probabilistic estimation methods, considering zero gate delay model [3,4,5] and real gate delay model [6,7] were proposed. The method presented in [5] is the most accurate assuming zero delay gate model since all types of correlations among the circuit signals are considered. The temporal correlation was captured by modelling the behaviour of a signal as a two state ....

F. Najm, "Transition Density: A new measure of activity in digital circuits," in IEEE Trans. On CAD, Vol. 12, No. 2, pp. 310-323, February 1995.

....such as the average steady state and the average transition probability of the circuit nodes, are used in order to evaluate the transitions of any circuit node. The above methods can be classified according to assumed gate delay model in the following categories i) the zero delay methods [3] [6] where only the functional transitions are considered and the ii) real gate delay methods [7] 9] where both the functional and spurious transitions are taken into account. Hence, real gate delay model is needed for accurate power estimation. In addition temporal correlation, input pattem ....

F. Najm, "Transition Density: A new measure of activity in digital circuits," in IEEE Trans. on CAD, Vol. 12, No. 2, pp. 310-323, February 1995.

....such synthesis methods contain two essential components power estimation, and optimization guided by the cost function. Power Estimation Model: In a digital CMOS circuit, dynamic power consumption is the dominant source of power consumption. The amount of energy dissipated in a CMOS circuit [13, 18] is approximately equal to the energy required to charge or discharge the load capacitances at various nodes in the Boolean network. If the circuit is controlled by a global clock, then the estimated average power dissipated is given by (0:5 Theta C l i Theta V dd ) Theta E i =T c (1) E ....

.... Hence, for optimization, the following cost function can be used: p i (1 Gamma p i ) Theta C l i (2) p i is the signal probability of node i and C l i is the load capacitance at node i The product p i (1 Gamma p i ) is called the switching activity (denoted as transition density in [13]) E i of node i. The power is directly proportional to the value of the total switched capacitance in the circuit. Throughout the remainder of this paper, the term switched capacitance will be used instead of the total power. The switched capacitance will be used in the cost function during ....

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F. Najm, "Transition Density: A new measure of Activity in digital circuits," IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems, Feb 1993.

....dissipation and be able to accurately estimate their power dissipation. Power dissipation in CMOS VLSI circuits is a direct function of the number of signal transitions occuring at the capacitive nodes present in it. The terms switching activity, transition probability [20] transition density [19] and transition activity [10] have been proposed in the past to provide a measure of the number of signal transitions. Switching activity and transition probability indicate the average number of transitions at a node per clock cycle. The term transition density equals the average number of ....

....been employed in [10] to indicate the average number of transitions in a clock cycle present in a bit of a signal word, in a word, and within a module. Here, we will employ the terminology transition activity as in [10] without any ambiguity. At the logic and circuit levels, techniques such as [13 15,17, 19, 29, 32] exist for power estimation. While these techniques provide accurate estimates of power dissipation, they require a gate or transistor level description of the circuit. Therefore, such techniques are applicable once the design has reached a substantial degree of maturity. Our interest in this ....

F. Najm, "Transition density, a new measure of activity in digital circuits," IEEE Transactions on Computer- Aided Design, vol. 12, no. 2, pp. 310-323, February 1993.

....sources can be mapped to the out degree and the wire length of the network topology. 2) Switching power describes the power dissipation of charging and discharging the node capacitance (3) The transition density is the average number of transitions per time [11]. It refers to whether a node is used or not during a data transfer performed on the network. This is depending on the routing of the network and the data transfer itself. The fanout corresponds to the out degree of the node. The load capacitance can be formed of the gate capacitance ....

F. N. Najm. Transition Density: A New Measure of Activity in Digital Circuits. IEEE Transactions on Computer Aided Design of Intergrated Circuits and Systems, pages 310--323, February 1993.

....of a wire i.e. the wire to metal layer capacitance . Therefore, with these coupling effects in mind, the number of switching activities on a bus (i.e. all transitions on all bus lines) do not necessarily reflect the power energy that is consumed by the bus. However, this was true (see [1]) for non deep sub micron designs . Hence, encoding mechanisms for bus power energy reduction that solely rely on minimizing the number of transitions are not efficient any more. In fact, any efficient encoding scheme for deep sub micron buses should be based on a precise physical bus model. ....

F.N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Tr. on CAD, Vol 12, No. 2, pp. 310--323, Feb. 1993.

....proposed in [1] to restructure the logic while keeping the existing placement solution minimally perturbed. 2. Preliminaries In this section, we first review the ratio based degradation model from [16] 20] followed by the probabilistic switching estimation technique from [10] and the functional symmetry based rewiring technique of [1] Let and be the fresh and aged pin to pin signal delays. is the aged to fresh signal delay ratio which characterizes the overall degradation of all transistors in the gate due to hotcarrier effect. These variables are defined for each ....

....extended pin to pin delay model, full chip timing reliability simulation is demonstrated to be 2 to 4 orders of magnitude faster[20] while accuracy is within 1 of the transistor level counterpart. Najm introduced the notion of equilibrium probability and transition density for power estimation[10]. The equilibrium probability of a signal x, denoted P(x) is the fraction of time x is evaluated to logic 1. The transition density of x, denoted D(x) is the average number of transitions per unit time. Under spatial and temporal independence assumption, an efficient algorithm was introduced to ....

[Article contains additional citation context not shown here]

F. N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, Feb, 1993, pp. 310-323

....Work Power estimation and modeling attract a lot of attention as power becomes one of the critical constraints for system design. Extensive research efforts have been put to develop efficient and accurate algorithms and tools at all levels of the design process, from circuit level [4] gate level [9, 10], RT level [7, 3] to system level [13, 12] Power is measured directly or by means of circuit activities like effective capacitances [7] and average currents[1, 6, 14] Most of them are simulation oriented, in which the system s power behavior is monitored during the simulation on the input ....

F.N. Najm. Transition Density: A New Measure of Activity in Digital Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.14, No. 1, pp. 310-323, 1993.

....literature for average power estimation. Fig. 1 shows the various simulative and nonsimulative methods in the literature. The probabilistic techniques are pattern dependent. The input vectors are randomly generated and applied to the model of the circuit until the desired accuracy is achieved. In [3], the signal probabilities provided by the user, are propagated through the circuit and the power at each node is computed based on the temporal dependence assumption. The CREST model [4] makes use of probability waveforms instead of discrete probability values. An efficient algorithm is proposed ....

F N Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.12, No.2, pp. 310-323, Feb 1993.

....circuit [1] a structural transformation based approach holds great promise for low power design. In this paper, we describe an efficient estimation tool that can be employed in high level synthesis for power optimization. Although a number of power estimators have been reported in the literature [1, 3, 4, 5, 9, 12, 7], with the exception of [1] 5] and [12] the others require the circuit to be specified at gate level. While flattening an RTL netlist into a gate level netlist is by itself a cumbersome task, gate level power estimators place excessive run time and memory requirements. Estimators reported in ....

....(a) signal probability expressions for each output line of the module and (b) an expression for power dissipationin the module type. These expressions are in terms of signal probabilities of the primary inputs to the module, the capac 1 Ref. Technique Type Glitch CorrelaPower tions [9] Transition Comb. No No Density Only [3] Transition Both Yes Yes Probability [14] Signal Both No Yes Probability [7] lag 1 Markov Comb. No Yes chain Only Table 1: Summary of Recent Gate level Power Estimators itances at the nodes of the module, and the operational frequency of the module. ....

F. Najm. Transition density: A new measure of activity in digital circuits. IEEE Transactions on CAD of Integrated Circuits and Systems, 12(2):310--323, February 1993.

....of a wire i.e. the wire to metal layer capacitance . Therefore, with these coupling effects in mind, the number of switching activities on a bus (i.e. all transitions on all bus lines) do not necessarily reflect the power energy that is consumed by the bus. However, this was true (see [1]) for non deep sub micron designs . Hence, encoding mechanisms for bus power energy reduction that solely rely on minimizing the number of transitions are not efficient any more. In fact, any efficient encoding scheme for deep sub micron buses should be based on a precise physical bus model. ....

F.N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Tr. on CAD, Vol 12, No. 2, pp. 310--323, Feb. 1993.

....trivial. Indeed, a whole set of solutions have been proposed, ranging from approaches which build the global ordered binary decision diagrams (OBDD s) 8] and, therefore, capture all internal dependencies, to efficient techniques which partially account for dependencies in an incremental manner [9] [12] The authors have pointed out the importance of correlations not only inside the target circuit, but also at its primary inputs [13] We will refer to this issue as the input problem and mention that it is important not only in power estimation, but also in low power design. Generating a ....

F. N. Najm, "Transition density: A new measure of activity in digital circuits," in IEEE Trans. Computer-Aided Design, vol. 12, pp. 310--323, Feb. 1993.

....in a distributed memory environment. Only static partitioning algorithms are considered in this dissertation. The workload of simulations can be characterized as number of events. This estimate is normally obtained from real sequential simulation [20, 102] or modeled by using probability analysis [1, 18, 32, 75, 101]. It is difficult to obtain accurate apriori estimates of the computational loads of processes and the communication frequency on various arcs of a circuit graph. Due to this difficulty, two kinds of real sequential simulation runs are used, one using estimates from a pre simulation and the ....

Farid N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits," IEEE Trans. on Computer-Aided Design, Vol. 12, No. 2, pp. 310-323, February 1993.

....In [8] power is minimized by modifying the function of each node in the circuit. Re encoding of a sequential circuit [9] and using gated clocks [10] are two techniques for power reduction in sequential circuits. Different activity metrics, mostly statistical such as in those presented in [11] and [12] have been defined and used for multi level logic network optimization for low power [13] synthesis of DSP circuits [14] and synthesis environment [15] 16] A low power logic synthesis method for XOR based circuits is presented in [17] and an architectural analysis method is in [18] ....

F. Najm, "Transition Density: A New Measure of Activity in Digital Circuits," IEEE Trans. on CAD, Feb. 1992.

....on the probabilities. Based on this, probabilistic simulation [50] 52] was proposed which accepts the specification of probability waveforms. It was further enhanced for more accuracy by Stamoulis et al. 10 [53]and Tsui et al. 54] Other probabilistic approaches based on transition density [23] and on Binary Decision Diagrams (BDDs) 31] are proposed. All the above approaches are applicable only for combinational circuits. For sequential circuits various approaches [56] 59] have been proposed which assume that the future of FSM is dependent only on its present state and independent ....

F. N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Trans. CAD, vol. 12, no. 2, pp. 310-323, February 1993.

....diminishing feature sizes are just a few of the trends that necessitate efforts in reducing power consumption of digital circuits. Apart from the problems of battery life and efficient heat sinking, dissipated power also significantly impacts circuit reliability. According to one researcher [Najm93], CMOS circuit runtime failures are most often related to dynamic circuit activity, which is one of the main causes of power dissipation. An extensive study of power dissipation in application specific integrated circuits (ASICs) Fren91] concludes that excessive power dissipation in a circuit ....

F. N. Najm, "Transition Density, A New Measure of Activity in Digital Circuits", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12. No. 2, Feb. 1993, pp. 310-323

....glitching severity typically increases with combinational depth. Thus, a node with shallow depth is likely to experience less glitching than a deep node, even if the number of path lengths to the two nodes is similar. The propagate term of (3) borrows ideas from the concept of transition density [8] and uses the notions of Boolean difference and static probability, which we briefly review here. The Boolean di#erence of a function, y = f(x1 , x2 , xn ) with respect to one of its inputs, x i , is defined as: fx i fx i (7) where fx i (fx i ) is the Boolean function obtained by ....

F. Najm. Transition density: A new measure of activity in digital circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 12:310--323, February 1993.

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F. N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits," IEEE Trans. on CAD, vol. 12, pp. 310-323, Feb. 1993.

....of the logic signal. This process, 4 which we call a companion process, embodies all the details of the logic signal, including its probability and density. Details and basic results related to the companion process are given in appendix A. 2 as an extension of previous continuous time work [9]. Specifically, the companion process is stationary, and for any time instant k, the probability that x(k) is high is equal to the signal probability of the logic signal: Pfx(k) 1g = P (x) 2) This result holds for any logic signal. If we (conceptually) construct the companion processes ....

....and let x(k) k 2 Z, be a function of discrete time that takes the values 0 or 1. We use such time functions to model discrete time logic signals in digital circuits. The definitions and results presented below represent extensions of similar concepts developed for continuous time signals [9]. The main results, propositions 1 and 3, are therefore given without proof. In proposition 2 we present a bounding relationships between probability and density for discrete time signals. A.1 Probability and Density Notice that the set of integers fbK 2c 1, b K 2cg contains exactly K ....

F. Najm, "Transition density: a new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 12, no. 2, pp. 310-323, February 1993.

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F. Najm, "Transition Density: A New Measure of Activity in Digital Circuits," IEEE Transactions on CAD, Vol. 12, No. 4, pp. 310-323, 1993.

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F. N. Najm, `Transition Density: A New Measure of Activity in Digital Circuits', IEEE Transactions on CAD, vol. 12, no. 2, pp. 310-323, Feb. 1993.

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F. N. Najm. "Transition density: A new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(2):310--323, February 1993.

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F. Najm, "Transition Density: A New Measure of Activity in Digital Circuits," IEEE Transactions on CAD, Vol. 12, No. 4, pp. 310-323, 1993.

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F. N. Najm. Transition density: A new measure of activity in digital circuits. ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(2):310--323, February 1993.

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F. N. Najm, `Transition Density: A New Measure of Activity in Digital Circuits', IEEE Transactions on CAD, Vol. 12, No.2, pp. 310-323, Feb.1993.

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F. Najm, "Transition Density: A New Measure of Activity in Digital Circuits," IEEE Trans. on CAD, Vol. 12, No. 4, pp. 310-323, 1993.

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F. N. Najm. " Transition density: A new measure of activity in digital circuits. " IEEE

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F. Najm, "Transition density: A new measure of activity in digital circuits." IEEE Transaction on Computer-Aided Design, vol. 12, 1993. 9

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F. Najm "Transition Density: A new measure of Activity in Digital Circuits" in IEEE Transaction on Computer-Aided Design Vol.12, No.2 (1993)

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Farid N. Najm. Transition density: A new measure of activity in digital circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 12(2):310--323, February 1993.

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F. N. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design , vol. 12, pp. 310--323, Feb. 1993.

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F. N. Najm, `Transition Density: A New Measure of Activity in Digital Circuits', IEEE Transactions on CAD, Vol. 12, No.2, pp. 310323, Feb.1993.

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F. N. Najm. " Transition density: A new measure of activity in digital circuits. " IEEE 12(2):310-323, February 1993.

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F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design, vol. 12, pp. 310--323, Feb. 1993.

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F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design, vol. 12, no. 2, pp. 310--323, Feb. 1993.

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F. Najm. Transition Density: A New Measure of Activity in Digital Circuits. IEEE Transactions on Computer-Aided Design, 12(2):310--323, February 1993.

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F. Najm. Transition Density: A New Measure of Activity in Digital Circuits. IEEE Transactions on Computer-Aided Design, 12(2):310-- 232, February 1993.

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F. Najm. Transition Density: A New Measure of Activity in Digital Circuits. IEEE Transactions on Computer-Aided Design, 12(2):310--323, February 1993.

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F.N. Najm, Transition Density: a New Measure of Activity in Digital Circuits, IEEE Trans. On CAD of Integrated Circuits and Systems, Vol.12,No.2, Feb.93.

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F.N. Najm, "Transition Density: A New Measure of Activity in Digital Circuits", IEEE Trans. on CAD, Feb. 93, pp. 310-323.

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Farid N. Najm. Transition Density: A New Measure of Activity in Digital Circuits. IEEE Transactions on ComputerAided Design, CAD-12(2):310--323, February 1993.

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F. N. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Transactions on Computer-Aided Design, vol. 12, pp. 310--323, Feb. 1993.

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F. Najm, "Transition density: A new measure of activity in digital circuits," Transactions on Computer-Aided Design, vol. 12, pp. 310--323, February 1993.

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F. N. Najm, "Transition density: a new measure of activity in digital circuits", IEEE Trans. Computer-Aided Design of Integrated Circuits and Syst. 14, 1 (1993) 310--323.

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F. N. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design, vol. 12, pp. 310--323, Feb. 1993.

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F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design, vol. 12, no. 4, pp. 310--323, 1993.

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