D. Liu et al., "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663--670, June 1994. Home/Search Document Not in Database Summary Related Articles Check |
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Efficient RTL Power Estimation for Large Designs - Ravi, Raghunathan, Chakradhar (Correct)
....estimates for parameters, such as gate count, switching activity, etc. leaving a lot to his her judgment. While such techniques are error prone in general, they may be accurate for some parts of a chip for which the complexity parameters are easy to estimate (e.g. memories and clock networks [4]) A class of analytical techniques, called information theoretic approaches, estimate average activity and capacitance factors for logic blocks based on the entropy of their input and output signals [5, 6] Enhancements to these approaches include consideration of the effect of area delaypower ....
D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663--670, June 1994.
A Survey of Techniques for Energy Efficient On-Chip.. - Raghunathan.. (2003) (2 citations) (Correct)
....swing signaling, Buffer sizing Current mode signaling SoC COMMUNICATION ARCHITECTURE ENERGY EFFICIENT RELIABLE Figure 1: SoC interconnect architecture optimization involves all layers of the design hierarchy 1. INTRODUCTION Interconnect wires account for a significant fraction (up to 50 [1]) of the energy consumed in an integrated circuit, and this fraction is only expected to grow in future. In fact, it is projected that, as technology scales to the nanometer regime, the delay and energy consumption of global interconnect structures will prove to be a major bottleneck for SoC ....
D. L. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips", IEEE Journal SSC, volume 29, issue 6, pp. 663--670, June 1994.
Static Energy Reduction Techniques in Microprocessor Caches - Hanson, Keckler, Burger (2001) (11 citations) (Correct)
....in the cache, the dynamic energy cost of a miss would be lower. However, each cache access would be slower, reducing system performance. We estimate the energy to drive the I O pins to fetch data from off chip memory with a simple model based on the following equation: Epi, 1. 3 Cpi, Vpin 2 [16]. We set Cp = 10pF, according to the multi chip module estimates in [16] and use an I O pin supply voltage of Vpi. 1.5V [17] With 32 address pins switching, the energy cost is 0.9nJ per off chip access. We account only for the pin energy that is expended in driving the address to the pins of ....
....each cache access would be slower, reducing system performance. We estimate the energy to drive the I O pins to fetch data from off chip memory with a simple model based on the following equation: Epi, 1. 3 Cpi, Vpin 2 [16] We set Cp = 10pF, according to the multi chip module estimates in [16] and use an I O pin supply voltage of Vpi. 1.5V [17] With 32 address pins switching, the energy cost is 0.9nJ per off chip access. We account only for the pin energy that is expended in driving the address to the pins of the CPU, and not energy expended to receive data. Static energy is ....
D. Liu and C. Svensson. Power consumption estimation in CMOS VLSI chips. IEEE Journal of Solid-State Circuits, 29(6):663-660, June 1994.
Low Power Error Resilient Encoding for on-Chip Data Buses - Bertozzi, Benini, De Micheli (2002) (7 citations) (Correct)
....margins decrease, raising concerns on the reliability of data transfers across wires [6] This problem is closely related to another major issue of ICs design: power consumption. Wires have been shown to account for a remarkable percentage of the total on chip power dissipation (up to 40 or 50 ) [9]. A straigthforward solution is the reduction of the voltage swing of signals propagated across interconnections. This requires the design of low swing interfaces, that can also be combined with the use of low supply voltages to achieve a larger power reduction [17] 14] All these trends force ....
D. Liu et al. "Power Consumption Estimation in CMOS VLSI Chips". IEEE Journal of Solid-State Circuits, 29:663-- 670, June 1994.
A Unified Energy Estimation Framework with.. - Vijaykrishnan.. (Correct)
....the data for the Cypress CY7C1326 133 SRAM chip. While the SimplePower framework models the influence of the clock inputs on all components of the architecture, it does not capture the energy consumed by the clock generation and clock distribution network. Existing clock energy estimation models [20, 21] require physical dimension of the design that can be obtained only after physical design and are difficult to estimate in the absence of structural information. However, we realize that this is an important additional component of the system energy consumption and we plan to address this in ....
D. Liu and C. Svensson, "Power consumption estimation in cmos vlsi chips," IEEE Journal of Solid-State Circuits, page 663, June 1994.
The Design and Use of SimplePower: A Cycle-Accurate .. - Ye, Vijaykrishnan, .. (2000) (39 citations) (Correct)
....Chau [15] is a fixed activity macro modeling strategy called the Power Factor Approximation (PFA) method. The energy models are parameterized in terms of complexity parameters and a PFA proportionality constant. Similar schemes were also proposed by Kumar et al. in [8] and Liu and Svensson in [11]. This approach assumes that the inputs do not affect the switching activity of a hardware block. To remedy this problem, activity sensitive empirical energy models were developed. These schemes are based on predictable input signal statistics; an example is the method proposed by Landman and ....
D. Liu and C. Svensson. Power consumption estimation in cmos vlsi chips. IEEE Journal of Solid-State Circuits, page 663, June 1994.
System Level Power-Performance Trade-Offs in.. - Puttaswamy, Choi, .. (2002) (Correct)
....accurately models the specific RISC processor as the measurements are based on cycle accurate functional simulations and Register Transfer Level hardware models used along with an actual technology library. An additional aspect of our work is the inclusion of power models for both off chip memory [19] and the Printed Circuit Board bus. 4. EXPERIMENTAL INFRASTRUCTURE We consider an embedded system which consists of a classic five stage pipeline RISC processor core with 4 kilobytes of instruction cache, 4 kilobytes of data cache, a single off chip synchronous SRAM memory of size 0.5 Megabytes ....
....average power dissipation reduces quadratically. As the switching frequency decreases, the average power dissipation decreases almost linearly. Note that the simultaneous halving of both voltage and frequency results in cubic savings. 4. 3 Memory Power Analysis We use an analytical SRAM model [19] for the off chip memory and cache power dissipation. For the off chip memory power model, we updated the analytical model [19] using the TSMC 0.25 process technology parameters. We use the switching activity from simulations to obtain estimates for SRAM memory power dissipation. The variation ....
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D. Liu and C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips," IEEE Journal of Solid-State Circuits, Vol. 29, No. 6, pp. 663-670, June 1994.
Low-Swing On-Chip Signaling Techniques: - Effectiveness And Robustness (Correct)
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D. Liu et al., "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663--670, June 1994.
Power Simulation and Estimation in VLSI Circuits - Pedram (1999) (2 citations) (Correct)
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D. Liu, C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips," IEEE Journal of Solid State Circuits, Vol. 29, No. 6, pp. 663-670, 1994.
Advanced Power Estimation Techniques - Pedram (1997) (3 citations) (Correct)
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D. Liu and C. Svensoon. "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid State Circuits, 29(6):663--670, June 1994.
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997) (22 citations) (Correct)
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D. Liu, C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips," IEEE Journal of Solid State Circuits, Vol. 29, No. 6, pp. 663-670, 1994.
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D. Liu and C. Svensson. Power consumption estimation in CMOS VLSI chips. ieee Journal of Solid State Circuits, 29(6):663--670, 1994.
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997) (22 citations) (Correct)
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D. Liu, C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips," IEEE Journal of Solid State Circuits, Vol. 29, No. 6, pp. 663-670, 1994.
Cycle-Accurate Macro-Models for RT-Level Power Analysis - Qinru Qiu Qing (1997) (18 citations) (Correct)
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D. Liu and C. Svensoon, "Power consumption estimation in CMOS VLSI chips", IEEE Journal of Solid State Circuits, vol. 29, pp.663-670, Jun. 1994.
An Adaptive Low-power Transmission Scheme for On-chip.. - Worm, Ienne, Thiran, De.. (2002) (4 citations) (Correct)
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D. Liu and C. Svensson. Power consumption estimation in CMOS VLSI chips. IEEE Journal of Solid-StateC ircuits,29(6):663--70,June 1994.
Static Energy Reduction Techniques for Microprocessor.. - Hanson, Hrishikesh.. (2001) (11 citations) (Correct)
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D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE Journal of Solid-State Circuits, vol. 29, no. 6, pp. 663--660, June 1994.
Static Energy Reduction Techniques in Microprocessor Caches - Heather Hanson Stephen (2001) (11 citations) (Correct)
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D. Liu and C. Svensson. Power consumption estimation in CMOS VLSI chips. IEEE Journal of Solid-State Circuits, 29(6):663--660, June 1994.
Low-Swing On-Chip Signaling Techniques: Effectiveness and.. - Zhang, George, Rabaey (2000) (8 citations) (Correct)
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D. Liu et al., "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, pp. 663--670, June 1994.
Gate-Level Power and Current Simulation of CMOS.. - Bogliolo, Benini.. (1997) (1 citation) (Correct)
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D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuit, vol. 29, no. 6, pp. 663--670, 1994.
An Adaptive Low-power Transmission Scheme for On-chip.. - Worm, Ienne, Thiran, De.. (2002) (4 citations) (Correct)
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D. Liu and C. Svensson. Power consumption estimation in CMOS VLSI chips. IEEE Journal of Solid-StateC ircuits,29(6):663--70,June 1994.
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D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 663--670, June 1994.
CACO-PS: A General Purpose Cycle-accurate Configurable.. - Antonio Beck Julio (Correct)
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D. Liu, C. Svensson. "Power Consumption Estimation in CMOS VLSI Chips". IEEE Journal of Solid-State Circuits, vol. 29, no. 6, 1994, pp. 663-670
Unknown - Power Optimization Of (Correct)
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D. Liu and C. Svensson. Power consumption estimation in cmos vlsi chips. IEEE Journal of Solid-State Circuits, 29(6):663--670, June 1994.
Code Coverage-Based Power Estimation Techniques For Microprocessors - Qu (2002) (Correct)
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D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips", IEEE J. Solid-State Circuits 29, 6 (1994) 663--670.
Energy-Driven Integrated Hardware-Software.. - Vijaykrishnan.. (2000) (45 citations) (Correct)
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D. Liu and C. Svensson. Power consumption estimation in cmos vlsi chips. IEEE Journal of Solid-State Circuits, page 663, June 1994.
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