L. Benini, G. De Micheli, "State Assignment for Low Power Dissipation, " IEEE Journal of Solid State Circuits, Vol. 30, No. 3, pp. 258-268, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....overhead to achieve 80 savings in power dissipation. 1. Introduction Minimization of power dissipation in VLSI circuits is important to improve the reliability and reduce packaging costs. While many techniques have investigated power minimization during the normal (functional) mode of operation [2, 4, 8, 12, 13, 17 19], it is essential to examine the power dissipation during the test mode of operation mainly for the following two reasons. Firstly it was outlined in [22] that power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the ....

....sequence. The low correlation between consecutive test vectors during test application leads to substantially higher power dissipation when compared to functional operation. c. Low power sequential circuits are synthesized by state assignment algorithms which use state transition probabilities [4, 8, 17, 19]. The state transition probabilities are computed assuming input probability distribution and state transition graph which is valid during functional operation. These two assumptions are not valid during the test mode of operation when scan design for testability (DFT) technique is employed. While ....

L. Benini and G. D. Micheli. State assignment for low power dissipation. IEEE Journal of Solid-State Circuits, 30(3):258--268, Mar 1995.

.... between consec utive test patterns during test application may lead to higher switching activity and hence power dissipation when compared to functional operation [191] b) Low power sequential circuits are synthesised by state assignment algorithms which use state transition probabilities [17, 18, 20, 42, 123, 168, 184]. The state transition probabilities are computed assuming the input probability distribution and the state transition graph which are valid during functional operation. These two assumptions are not valid during the test mode of operation when scan DFT technique is employed. While shifting out ....

L. Benini and G. De Micheli. State assignment for low power dissipation. IEEE Journal of Solid-State Circuits, 30(3):258--268, March 1995.

....observable. Observing the controller and datapath faults separately, in general, implies more test time (due to separate test session) and more overhead (due to direct observation of each) Recently, the effect of controller design on power consumption has been explored in [ 15] The work of [3] uses special state assignments to reduce power, while [4] adds some combinational logic to the original controller to avoid inactive state transitions. to block the global clock and effectively turn off the inactive components in the datapath. 2 Background Two approaches can be taken to ....

L. Benini and G. DeMicheli, "State Assignment for Low Power Dissipation, " Proc. of the IEEE Custom Integrated Circuits Conf., May 1994.

....tool is included in the SIS system [6] 2.2 Approaches for Low Power State Encoding Main works in low power FSMs compute first the switching activity and transition probabilities [7] The key idea is the reduction of the average activity by minimizing the bit changes during state transitions. In [8], a probabilistic description of the state machines is used. Then, the state assignment minimizes the Hamming distance between states with high transition probability. To obtain the probabilistic behavior of a general FSM, the STG is modeled as a Markov Chain, and the state algorithm problem is ....

L. Benini and G. De Micheli. State Assignment for Low Power Dissipation. IEEE Journ. of Solid State Circuits, Vol. 30, No. 3, pp. 258-268, March 1995.

....switching activity in two ways: either by disabling the input data to the FSM, or by blocking the state registers. The cost is an extra hardware to detect certain conditions to stop parts of the machine. The experiments presented in this paper are based on the ideas proposed in [7] 15] 6] 3][4], adapted or modified to suit well with the technological target: LUT based FPGAs. The original FSM is divided into two sub FSMs. Each submachine must to have roughly the same amount of states. A probabilistic approach is utilised to determine an optimal partition that guarantees a m mimum ....

....total transition probabilities PU can be calculated as: P ,j = Pi,j Pi Fig. 1. a) State Transition Graph (STG) b) steady state probabilities and total transition probability H.b. Low power design of FSM The most popular technique to reduce power in FSM is to modify the state encoding [27][4][16] 28] 14] These works are focused on the Hamming distance minimization of the most probable state transitions. However, this solution usually increases the required logic to decode the next state. Then, a tradeoff between switching reduction and extra capacitance exists. In the area of FPGAs, ....

L.Benini and G. De Micheli. State Assignment for Low Power Dissipation. IEEE Journ. of Solid State Circuits, Vol. 30, No. 3, pp. 258-268, March 1995.

....for such a system. In CMOS circuits, power is dissipated in a gate when the gate output changes from 0 to 1 or from 1 to 0. Minimization of power dissipation can be considered at algorithmic, architectural, logic and circuit levels [6] Studies on low power design are abundant in the literature [7, 8, 9, 10, 11, 12, 13] in which various techniques were proposed to synthesize designs with low transitional activities. Recently, new research directions in reducing power consumptions have begun to address the issues of arranging software at instruction level to help reduce power consumptions [14, 15] To be ....

Luca Benini, and G. De Micheli, "State Assignment for Low Power Dissipation", IEEE Journal of Solid State Circuits, Vol. 30, no. 3, pp.258-268, March 1995.

.... State Transition Probabilities Given the FSM description and the input probabilities, the first step of our estimation consists of the computation of the total state transition probabilities for each edge in the graph, by modeling the FSM as a Markov chain and following the same method shown in [3, 15, 22]. Let the FSM, composed of n s states, described by using a STG composed of n s vertexes, corresponding to the states in the set S = s 1 , s 2 , s nS , and the related directed edges. The edges are labeled with the set of input configurations that cause a transition from the source state to ....

....state to the destination state. Considering a transition from state s i to state s j , we can compute the factor p ij , called conditional state transition probability, that represents the conditional probability of the transition from state s i to state s j , given that the FSM was in state s i [3]: p ij = Prob (Next = s j Present = s i ) The computation of the p ij s can be carried out as in [15] assuming totally independent primary inputs PI = x 1 , x 2 , x k , x nI and being p xk the static signal probability of input x k . Let f ij (x 1 , x 2 , x k , x nI ) ....

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L. Benini and G. De Micheli, State Assignment for Low Power Dissipation, IEEE Journal of Solid State Circuits, 30 (3) (1995) 258-268.

....techniques to improve controller area or performance. The importance of state assignment is discussed in [DeMicheli et al. 1984] and [Devadas et al. 1988] among others. Recently, the effect of controller design on power consumption has been explored in [Landman and Rabaey 1995] The work of [Benini and DeMicheli 1994] uses special state assignments to reduce power, while [Benini et al. 1994] adds some combinational logic to the original controller to avoid inactive state transitions. For self testable designs based on BIST (Built In Self Test) research involving controllers focuses on test plan and test ....

....assignment is discussed in [DeMicheli et al. 1984] and [Devadas et al. 1988] among others. Recently, the effect of controller design on power consumption has been explored in [Landman and Rabaey 1995] The work of [Benini and DeMicheli 1994] uses special state assignments to reduce power, while [Benini et al. 1994] adds some combinational logic to the original controller to avoid inactive state transitions. For self testable designs based on BIST (Built In Self Test) research involving controllers focuses on test plan and test scheduling [Abadir and Breuer 1985] Kime and Saluja 1982] Jone et al. 1989] ....

Benini, L. and DeMicheli, G. 1994. State assignment for low power dissipation. In Proc. IEEE Custom Integrated Circuits Conf. (1994). 136--139.

....overhead to achieve 80 savings in power dissipation. 1. Introduction Minimization of power dissipation in VLSI circuits is important to improve the reliability and reduce packaging costs. While many techniques have investigated power minimization during the normal (functional) mode of operation [2, 4, 8, 12, 13, 17 19], it is essential to examine the power dissipation during the test mode of operation mainly for the following two reasons. Firstly it was outlined in [22] that power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the ....

....sequence. The low correlation between consecutive test vectors during test application leads to substantially higher power dissipation when compared to functional operation. c. Low power sequential circuits are synthesized by state assignment algorithms which use state transition probabilities [4, 8, 17, 19]. The state transition probabilities are computed assuming input probability distribution and state transition graph which is valid during functional operation. These two assumptions are not valid during the test mode of operation when scan design for testability (DFT) technique is employed. While ....

L. Benini and G. D. Micheli. State assignment for low power dissipation. IEEE Journal of Solid-State Circuits, 30(3):258--268, Mar 1995.

....observable. Observing the controller and datapath faults separately, in general, implies more test time (due to separate test session) and more overhead (due to direct observation of each) Recently, the effect of controller design on power consumption has been explored in [15] The work of [3] uses special state assignments to reduce power, while [4] adds some combinational logic to the original controller to avoid inactive state transitions. to block the global clock and effectively turn off the inactive components in the datapath. 2 Background Two approaches can be taken to ....

L. Benini and G. DeMicheli, "State Assignment for Low Power Dissipation, " Proc. of the IEEE Custom Integrated Circuits Conf., May 1994.

....related research was first aimed at precise computation of switching activity in sequential circuits [11] 9] Since then several low power state encoding algorithms have been proposed. Tsui et al. 12] integrated cost functions for state register and transition logic activity, while Benini et al. [1] developed algorithms trading off accuracy vs. computational complexity. Chen et al. 2] already formulated the encoding problem as a hypercube embedding problem. Common to these and other approaches however is the limitation to a predetermined number of bits for the state encoding, which will be ....

....at least for medium sized problem instances, since all benchmark embeddings were generated within few minutes. 4 Results We have run our fast and greedy encoding algorithms on a set of MCNC FSM examples in kiss2 format. As a reference the O(#V #E) encoding algorithm pow3 presented by Benini [1] was selected, since it computes a minimum length encoding targeting low state register activity in a comparable small runtime. The results are summarized in table I. Columns 1 and 2 contain the circuit name and the number of states after elimination of unreachable and unleavable states. The ....

L. Benini and G. DeMicheli. State Assignment for Low Power Dissipation. IEEE Journal on Solid State Circuits, 11(4):32--40, March 1994.

....earlier work done in this area involved performing exhaustive simulations for randomly generated input sequences [1] 2] Although these methods gave accurate results, lengthy computation times rendered them impractical for large circuits. As a result researchers resorted to stochastic approaches [3] [15] where the probability of transition of nodes in the circuit is estimated. However, in many non portable applications some knowledge of the maximum power together with the average power is required in order to determine the nature of heat sinks. Moreover, a theoretical analysis of the ....

L. Benini and G. D. Micheli, "State assignment for low power dissipation", IEEE Journal of Solid-State Circuits, vol. 30, pp. 258--268, Mar. 1995.

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L. Benini and G. De Micheli, "State assignment for low power dissipation, " IEEE J. Solid-State Circuits, vol. 11, pp. 258--268, Mar. 1995.

....of the rows of E corresponding to the 1s in does not intersect any of the rows of E corresponding to the 0s in . The 0s in the relation matrix can then be considered as don t care in the constraint matrix. 3. 2 General Encoding Algorithm The problem of input encoding has been extensively studied ([1] [4] 7] 9] 10] 11] 12] 14] We use an approach reminiscent of MUSTANG [9] and POW3 [1] Definition 4. An affinity graph is an undirected weighted graph in which the nodes are the symbols and the edges are the relations between the symbols in . The weight on the edge , is defined as: ....

....to the 0s in . The 0s in the relation matrix can then be considered as don t care in the constraint matrix. 3. 2 General Encoding Algorithm The problem of input encoding has been extensively studied ( 1] 4] 7] 9] 10] 11] 12] 14] We use an approach reminiscent of MUSTANG [9] and POW3 [1]. Definition 4. An affinity graph is an undirected weighted graph in which the nodes are the symbols and the edges are the relations between the symbols in . The weight on the edge , is defined as: 5) where is the number of pointers, is the total number of symbols, the number of symbols in ....

[Article contains additional citation context not shown here]

L.Benini and G.De Micheli, "State assignment for low power dissipation" Custom Integrated Circuits Conference, 1994, pp. 136-139.

....of the finite state machine, shows that sizable power reductions can be obtained with our technique. 1 Introduction The majority of the currently published work in the area of automatic synthesis for low power focuses on the reduction of the level of activity in some portion of the circuit [3, 4, 5, 6], since in the dominant CMOS technology the most important fraction of the power is dissipated during switching events. In synchronous circuits, a very promising technique is based on selectively stopping the clock in portions of the circuit where active computation is not being performed. Local ....

....STG is shown in Figure 2 (b) The higher complexity in terms of states and edges of the Moore representation is evident. Notice that both FSMs are incompletely specified. 2. 2 Probabilistic models of FSMs We model the probabilistic behavior of a general FSM using a Markov chain [8] as done in [9, 6, 16]. This model can be described by a weighted directed graph with a structure isomorphic to the STG of the machine. For a transition from state s i to state s j , the weight p i;j on the corresponding edge represents the conditional probability of the transition (i.e. the probability of a ....

L. Benini and G. De Micheli, "State assignment for low power dissipation," in CICC, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 136--139, May 1994.

....continue to shrink, allowing more devices to fit on a chip, power consumption has taken on increased importance. Much recent work has focused on accurate estimation of power consumption and on its concomitant reduction at all levels of abstraction, from high level synthesis down to physical layout [1, 2, 3, 4, 5, 6, 7]. Most power reduction techniques have emphasized reducing the level of activity in some portion of the circuit. We extend this research by concentrating on reducing the activity level of the clock by selectively stopping the clock. Because many sequential machines are implementations of reactive ....

L. Benini and G. De Micheli, "State assignment for low power dissipation," in CICC, Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 136--139, May 1994.

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L. Benini, G. De Micheli, "State Assignment for Low Power Dissipation, " IEEE Journal of Solid State Circuits, Vol. 30, No. 3, pp. 258-268, 1995.

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L. Benini and G. D. Micheli, `State assignment for low power dissipation', IEEE J. of Solid-State Circuits, 30(3): 258-268, 1995.

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L. Benini, G. De Micheli, "State Assignment for Low Power Dissipation," IEEE Journal of Solid State Circuits, Vol. 30, No. 3, pp. 258-268, 1995.

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Benini, L. and Micheli, G. D.: `State assignment for low power dissipation', IEEE J. of Solid-State Circuits,

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L. Benini and G. De Micheli, `State Assignment for Low Power Dissipation ', in IEEE Journal of Solid State Circuits, vol.30, no.3, 1995.

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Benini,L.; De Micheli,G.: State Assignment for Low Power Dissipation. IEEE Journal for SolidState Circuits, Vol. 30, No. 3, March 95, pp. 32-40.

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L. Benini and G. De Micheli, "State assignment for low power dissipation," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 258--268, March 1995.

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L. Benini and G. De Micheli, "State assignment for low power dissipation, " IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 258--268, 1995.

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