| James C. Hoe. Network Interface for Message-Passing Parallel Computation on a Workstation Cluster. In Proceedings of Hot Interconnects II, August 1994. |
....the network, is context switched. The CM 5 adopts this solution [17] 3. User initiated transfers between memories can use explicit acknowledgements to manage senderside buffer space for each message. Software protocols such as IP typically use this approach. FLASH general messages and FUNet [11] provide the acknowledgements in hardware. 1.2 FUGU Overview FUGU provides hardware support for three communication mechanisms. A coherent shared memory system communicates implicitly via messages synthesized and interpreted by hardware. A user level messaging facility allows user code to send ....
James C. Hoe. Network Interface for Message-Passing Parallel Computation on a Workstation Cluster. In Proceedings of Hot Interconnects II, August 1994.
....The network and the network interface inform the sender whether its message has been successfully delivered (positive acknowledgement) or whether it has been discarded (negative acknowledgement) In the case of a negative acknowledgement, the sender eventually resends the message. FUNi [Hoe94] is a recent example of an acknowledgement driven network interface design. Our network interface could be modified to use an acknowledgment driven flow control, without necessarily modifying the programmer s view of the network interface. The network interface could maintain a pool of buffers ....
....do not reduce delays along critical paths. We believe that machines must reduce latency in addition to hiding it. Other researchers have addressed certain aspects of our communication framework before. The MEF [ADI83] Alewife [ACD 91] CM 5 [LAD 95] and the proposed T [NPA92] and FUNi [Hoe94] machines are among the many that have added a network interface to a commercial processor. Several NIs incorporate a subset of our NI optimizations. The CM 2 [Hil85] and iWARP [BCC 90] had a register mapped interface. In both cases, the interface consisted of a single register out of which a ....
James C. Hoe. Network interface for message passing parallel computation on a workstation cluster. In Proceedings of the 2nd Hot Interconnect, Stanford, California, August 1994.
....delivery of both the processing nodes, the network, and the processor network interface unit (NIU) Machines such as Flash [16] and Alewife [1] share goals similar to StarT Voyager s but are not open systems. Connecting the NIU to a standard I O bus is the typical way of providing an open system [2, 31, 4, 10, 3, 11], but current I O bridges severely limit the performance and do not expose enough processor cache state to build cache coherent DSM s. The multiple processor slots of SMP s make ideal attachment points and do not require modifications to the SMP architecture. However, cooperation with the SMP ....
J. C. Hoe. Network Interface for Message-Passing Parallel Computation on a Workstation Cluster. In Proceedings of Hot Interconnects II, Stanford, CA, pages 154 -- 163, Aug. 1994. 18
....designed to accommodate third party devices, is currently a popular approach. Commercial examples include machines like the IBM SP 1[21] and SP 2[2, 42] and plug in extensions like Myricom s Myrinet[5] and DEC s Memory Channel[18] while research efforts include Princeton s SHRIMP[4] and StarT Jr[19]. Most I O bus based message passing support utilizes main memory DRAM to house user level message queues. The NIU delivers message between such queues on different nodes. In some designs, messages are sent out by writing directly across the I O bridge chip to the NIU. Although these projects ....
J. C. Hoe. Network Interface for Message-Passing Parallel Computation on a Workstation Cluster. In Proceedings of Hot Interconnects II, Stanford, CA, pages 154 -- 163, Aug. 1994.
....to accommodate third party devices, is currently a popular approach. Commercial examples include machines like the IBM SP 1[22] and SP 2[2, 40] and plug in extensions like Myricom s Myrinet[5] and DEC s Memory Channel[19] while research efforts include Princeton s SHRIMP[4] and MIT s StarT Jr[20]. The chief drawbacks of this approach are the difficulties encountered when implementing aggressive cache coherent distributed shared memory, and lack luster message passing performance for fine grain communication. To overcome these deficiencies, StarT Voyager s network interface is located on ....
J. C. Hoe. Network Interface for Message-Passing Parallel Computation on a Workstation Cluster. In Proceedings of Hot Interconnects II, Stanford, CA, pages 154 -- 163, Aug. 1994.
....The specifics of the network implementation is contained within PLM. This modular design allows StarT jr to adopt a variety of different interconnect technologies with only limited modifications. 3 FUNi The basic FUNi message passing interface was first proposed for SBus equipped workstations[8]. The design proposed a way to implement a fine grain message passing interface on a peripheral bus without a penalty in communication overhead from the long access latency. The design required more intelligence in the interface hardware to manage a message passing interface in the host memory. ....
J. C. Hoe. Network interface for message-passing parallel computation on a workstation cluster. In Proceedings of Hot Interconnects II, August 1994.
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J. C. Hoe. Network interface for message-passing parallel computation on a workstation cluster. In Proceedings of Hot Interconnects II, August 1994.
....design should take these biases into consideration and use the available features to its advantage. FUNi2, Flexible User level Network Interface, is a second generation network interface design aimed at providing stock commercial workstation with an cost effective message passing interface [5]. FUNi2 follows a different approach to network interface design from the projects described. Instead of trying to reduce communication costs by tight coupling of exotic hardware, FUNi2 attempts to reduce the effects of communication overhead by decoupling the network interface from the ....
J. C. Hoe. Network interface for message-passing parallel computation on a workstation cluster. In Proceedings of Hot Interconnects II, August 1994.
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