W.D. Billowitch. IEEE 1164: Helping designers share VHDL models. IEEE Spectrum, 30(6):37, June 1993. Home/Search Document Not in Database Summary Related Articles |
This paper is cited in the following contexts:
Parallel Logic Simulation of VLSI Systems - Chamberlain (1995) (3 citations) (Correct)
....information. For example, many switch level simulators add an X state to represent unknown or floating signals, and gate level simulators add states to represent drive strength and high impedance conditions. The IEEE standard logic system for VHDL simulation (STD LOGIC 1164) uses a 9 valued logic [6]. There are a number of ways in which parallelism can be exploited to improve simulator performance. Algorithm parallelism uses pipelining techniques to accelerate the simulation loop by executing individual program steps on different processors (e.g. event queue management, functional ....
W.D. Billowitch. IEEE 1164: Helping designers share VHDL models. IEEE Spectrum, 30(6):37, June 1993.
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