S. Thakkar, P. Gifford, and G. Fielland. The Balance Multiprocessor system. IEEE MICRO, 57--69, February 1988.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....Multiprocessor systems are commonly classified into the following two categories: sharedmemory and distributed memory parallel computers. The shared memory machines provide all processors with access to a common global memory. Examples of such machines are the Alliant FX 2800, the Sequent Balance [74], the Cedar [45] and the IBM RP3 [19] machines. On a distributed memory machine (multicomputer) each processor has direct access to only a small part of the total memory, which is distributed among processors. Examples of such systems are the Connection Machine CM 5 [75] the Intel iPSC 860 ....

S. Thakkar, P. Gifford, and G. Fielland. The Balance multiprocessor system. IEEE Micro, pages 57--69, February 1988.

....to locate the owner of lines. 3.2 Cache line size, locality and false sharing The size of cache lines is a critical issue in cache based shared memory implementations. Small line sizes, of the order of a few tens of bytes, were usual in first generation bus systems such as the Sequent Balance [41]. Small lines had the advantage that few bus cycles were required to transfer a copy of a line, allowing as many as 30 processors to be used without contention for the bus becoming a limiting factor. This is possible because bus arbitration is so fast. Larger line sizes would have either required ....

Shreekant Thakkar, Paul Gifford, and Gary Fielland. The Balance multiprocessor system. IEEE Micro, 8(1):57--69, February 1988.

....work has focused on the development and implementation of snoopy protocols for single bus systems. The single bus protocols proposed differ mainly in the cache consistency policy used. Write through with invalidating caches is employed by the VAX 11 780 [Archibald 1984] the Sequent Balance 8000 [Thakkar 1988], and the Encore Multimax [Dubois 1988] In an attempt to limit the bus traffic arising from unnecessary invalidations, the SPUR multiprocessor [Hill 1986] and the Symmetry Multiprocessor [Lovett 1988] use write once with invalidating caches. Finally, the Xerox PARC Dragon [Atkinson 1987] and the ....

Thakkar, S., Gifford, P., and Fielland, G. (1988). The Balance Multiprocessor System. IEEE Micro, 8(1):57--69.

....between software model and underlying architecture will limit peak performance. A dominant characteristic of any shared memory machine is the manner in which PEs are connected with memories. Those with a small to moderate number of PEs can work well with either a crossbar [WuBe72] or a simple bus [ThGF88] [Hill86] However, in considering a highly parallel machine (with hundreds of PEs, for example) busses become too easily saturated and crossbars become too expensive. In constructing an N PE multiprocessor where N is large, a multistage network [GoLi73] Pate81] Gott87] can offer a good ....

....synchronization with the reduced network traffic of the busy waiting method. When a PE wants to signal the others, it first modifies the synchronization variable in memory and subsequently communicates this update to all the caches. Note the similarity here with Sequent s parallel spin locks [ThGF88] [LoTh88] and with the test test set primitive of [RuSe84] These latter methods are only applicable to bus based systems, however, whereas our technique is more generally suited to large scale parallel systems. In the following two sections, we present our methods for implementing this technique. ....

Shreekant Thakkar, Paul Gifford, and Gary Fielland, "The Balance Multiprocessor System," IEEE Micro, (8)1, February, 1988, pp. 57-69.

....have multiple instruction execution units and therefore operate on multiple data streams. MIMD architectures can be divided into two subclasses, tightly coupled and loosely coupled. Tightly coupled machines have multiple processors that can communicate and interact through shared memory [3]. Access to non local memory is usually on the same order of magnitude as a local access. Loosely coupled machines, however, have physically separate memory and communicate through a communication network [4] Loosely coupled machines usually have a smaller degree of interaction between processing ....

S. Thakkar and et al. The balance multiprocessor system. IEEE Micro, pages 57--69, feb 1988.

....A lock request is sent to a lock owner. If the lock is free, permission is granted; if busy, the request is queued. When the lock is freed, the next queued process gets permission. Lock queues can be supported in hardware[9, 15] or in software[10, 2, 16, 3, 18] Test and set with hardware support[20] is adequate on tightly coupled multiprocessors. Queue based locks are needed in distributed memory systems to minimize network traffic after lock release. On multicomputers connected by networks, locating the lock owner is an issue. Distributed directory schemes[15] allow a lock request to go ....

S. Thakkar, P. Gifford, and G. Fielland. The Balance Multiprocessor System. IEEE Micro, 8(1):57--69, Feb. 1988.

....Sequent Symmetry. In particular, application programs are assumed to be written using the Argonne Labs Parmacs library [124] Therefore macros similar to the Parmacs macros have been implemented [151] The resource management on the Symmetry is handled by a Unix like operating system called Dynix [192]. In Dynix, application processes can be forked and scheduled onto processors dynamically. These processes are heavy weight Unix (Dynix) processes. Therefore frequent creation and destruction of these processes is inefficient each context switch in Dynix can cost up to 55 msec [23] As a result, ....

S. Thakkar, P. Gifford, and G. Fielland. The Balance Multiprocessor system. IEEE MICRO, 57--69, February 1988.

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S. Thakkar, P. Gifford, and G. Fielland. The Balance Multiprocessor system. IEEE MICRO, 57--69, February 1988.

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S. Thakkar, P. Gifford, and G. Fielland, "The Balance Multiprocessor System," IEEE Micro, Vol.8, No.1, February 1988, pp.57--69.

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