J. Brzozowski and C.-J. Seger. Asynchronous Circuits. Springer, 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....operator with memory for discretevalued signals, the delay, which takes a signal and shifts it in time. One can define a variety of delay operators differing from each other in complexity and in physical faithfulness. The class of models that we consider is called bi bounded inertial delays [BS94] and is characterized by an interval I = l, u] which gives lower and upper bounds on the propagation delay. For the purpose of this paper we will use the model introduced in [MP95] but since the choice of the delay model is orthogonal to the rest of the methodology we will defer the exact ....

....performance of our technique (computation time and size of the reachability graph) as a function of the number of stages for three Another choice might be to join only intervals that have a non empty intersection. In fact, if we assume no lower bound on the delay (the up bounded model of [BS94] events can happen in any order. 10010 x1 time 01000 time time time 01111 z time time z time time exc y2 10 10 10 10 10 10 10 00 y2 : 20,30] 10 00 00 00 y2 : 20,30] 10 10 00 y2 : 20,30] 11 z : 20,40] 00 y2 : 20,40] 01 y2 ....

J.A. Brzozowski and C-J.H. Seger, Asynchronous Circuits, Springer, 1994.

.... that are currently working are a direct translation from job shop scheduling problems , a translation from flat timed automata in the Kronos format, and a global time compositional translation for the sub class of timed automata corresponding to digital circuits with bi bounded inertial delays [BS94] following their modeling as timed automata [MP95,BJMY] 6.2 Experimental Results Long Runs of Simple Automata As a first example we took a simple timed automaton with 4 states and one clock and created, via our translator, DL formulae for paths of varying length. Table 1 show how the size and ....

J.A. Brzozowski and C-J.H. Seger, Asynchronous Circuits, Springer, 1994.

.... internal wire by a series of inferences on the definition of the circuit (a precise statement is given in Section 2) Shiple [11] shows that constructive definitions are precisely those that are well behaved electrically, for any assignment of delay values, in the up bounded inertial delay model [4]. It is inefficient to check constructivity by enumerating all possible external valuations. Symbolic algorithms for checking constructivity [2, 12, 11] manipulate sets of input valuations, representing them with BDD s [3] This manipulation is based on simultaneous fixpoint equations derived ....

....of the order in which simplification steps are applied. The appropriateness of constructivity is shown by Shiple [11] who demonstrates that constructive definitions are precisely those that are well behaved electrically, for any assignment of delay values, in the up bounded inertial delay model [4]. Malik [9] shows that the problem of detecting semantic cyclicity is NP complete. Definition 1 (Constructivity) A simultaneous definition is semantically acyclic iff for each valuation of the external variables, the simplification process leads to an empty set of definitions. 3 Constructivity ....

J. A. Brzozowski and C-J. H. Seger. Asynchronous Circuits. Springer-Verlag, 1994.

....different delay models are assumed for the wires and the gates in an asynchronous circuit. For example, the operation of a class of asynchronous circuits is based on the zero delay model for wires and the unbounded delay model for gates. Formal definitions of the various delay models are given in [12]. A concept closely related to the delay model of a circuit is its mode of operation. The mode of operation characterizes the interaction between a circuit and its environment. Classical asynchronous circuits operate in the fundamental mode [13,14] which assumes that the environment changes only ....

....the boundeddelay model, and have, as primitive elements, gates that correspond to the basic logic functions, like and, or, and inversion. These formalisms are convenient for implementing logic functions, analyzing circuits for the presence of hazards, and synthesizing fundamental mode circuits [12, 14]. Event based formalisms deal with sequences of events rather than binary logic variables. Circuits designed with an event based formalism operate in the input output mode, under an unbounded delay model, and have, as primitive elements, the join, the toggle, and the merge, for example. ....

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J. A. Brzozowski and C.-J. H. Seger, Asynchronous Circuits. Springer-Verlag, 1995.

....The minimum and maximum circuit delays re ect the fact that a change to one of the inputs x may a ect the value of the output signal z no earlier than after time dmin.C and no later than after time dmax.C . Note that the calculated extrema may be pessimistic as estimates of the actual extrema (see [4], section 1.2) It is now possible to distinguish combinational circuits having the same functional speci cation but di erent timing behaviours. For example these two implementations of exor assume the delay of an and gate is a , that of an or gate is o and that of an inverter is i: texor0 = z ....

J. A. Brzozowski and C.-J. H. Seger, Asynchronous Circuits. Springer-Verlag, 1995.

.... in this paper does not need an adder at the last stage, since digits are generated in redundant form starting from the most significant ones and conversion into non redundant form may be performed on thefly [12] Synchronization is achieved by means of a dual rail encoding of the data bits [6]. This implies the use of differential logic. We choose to implement the basic cells using CPL gates [2] The use of complementary pass transistor gates is particularly appealing for low power applications. Moreover, CPL can be faster than conventional CMOS logic. Nevertheless, the reduced output ....

....design has been simulated using HSPICE. Prediction functions have been synthesized using Boolean relations [17] in order to produce a minimum cost function. In [8] we also prove that the designed cells have a monotonic behaviour. This is crucial to assure the correctness of the dual rail protocol [6]. To give technology independent estimations, delays and areas are normalized with respect worst case delay and area of an unloaded XOR XNOR gate. Area estimations take into account the area due to interconnections among the cells. It must be also pointed out that the proposedscheme, as well as ....

J. A. Brzozowski and C.-J. H. Seger. Asynchronous Circuits. Springer-Verlag, New York, 1994.

....formed by several pipelined stages. Each stage represents a radix 2 iteration step of the standard recurrence division [10] and operates as soon as the required operands arrive. Synchronization between adjacent stages is achieved by using DCVSL differential logic and a dual rail handshake protocol [2]. Each stage computes all the possible assimilations of the partial residual in advance, and since this number depends on the maximum quotient digit, this approach is clearly limited to radix 2. As mentioned previously, the use of a low radix is highly penalizing because it increases the number ....

....times by means of a very simple speculation and error detection and correction function and by a function that permits to switch to a higher radix when the divider input matches certain constraints. Synchronization is achieved by means of bundled data with a four phase handshake protocol [2]. This allows to implement division units with a reduced area since we avoid the use of differential logic with dual rail synchronization. We develop the method, evaluate alternative possibilities and present some examples of implementation, comparing them with the implementation of conventional ....

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J. A. Brzozowski and C.-J. H. Seger. Asynchronous Circuits. Springer-Verlag, New York, 1994.

....different notations and techniques for the specification and description of asynchronous designs. A detailed description of asynchronous design methodologies is beyond the scope of this thesis. In depth surveys of existing asynchronous methodologies may be found in [Broz89] Gopa90] Hauc93] [Broz95] and [Davi95] where comprehensive bibliographies are provided; additionally, the Asynchronous Online Bibliography (async bib win.tue.nl) provides continuous, up to date information regarding asynchronous research. The following section provides a short overview of the major and most influential ....

Brozowski, J. A., Seger, C-J., H., "Asynchronous Circuits", Springer Verlang, 1995.

....clock period and the skew between the receiver and transmitter. We model the uncertainty concerning the delay associated with gates using the bi bounded delay model, that is, we associate with every gate an interval [l; u] indicating the lower and upper bounds for its switching delay (see [L89] BS94] MP95] and [AMP98] for the exact definitions) Following [MP95] we can model any logical gate with a delay [l; u] using a timed automaton with 4 states (0 stable, 0 excited, 1 stable and 1 excited) and one clock. In particular, each stage of STARI is modeled by the three timed automata of ....

J.A. Brzozowski and C-J.H. Seger, Asynchronous Circuits, Springer, 1994.

....are called inertial models, whereas models where output transitions copy precisely the changes in the input excitation, as in Figure 13 (c) are called ideal models. Variations of these models and other CMOS gate models are also possible. For a detailed discussion of gate and delay models, see [BS95]. Situations where a CMOS gate becomes unstable and then stable again before undergoing an output transition, as in Figure 13, are called hazards. Since several behaviors of a gate may be expected in a hazard situation, we need to know whether hazards may occur and, if so, for which gates. One can ....

....above, but it leads to a goal state of the inertial model in Figure 15. The hazard intolerant models extend to arbitrary CMOS gates the asynchronous models used e.g. in [Di89] for Boolean gates, while the inertial models correspond to the widely known inertial delay models described e.g. in [BS95]. FIREMAPS provides operators for building CMOS gate models directly from the instability functions of the gates. These operators are (hazard intolerant) for the hazard intolerant model and (inertial) for the inertial model. Each of these operators takes as arguments a Boolean function ....

J. A. Brzozowski and C.-J. H. Seger. Asynchronous Circuits. Springer Verlag, 1995.

....shift register, signature analysis. 1. Introduction Asynchronous design methodologies are a subject of growing research interest since they appear to offer benefits in low power applications, promise greater design modularity and exhibit typical case performance rather than worst case performance [Lav93, Brzo95]. An asynchronous ARM6 microprocessor (AMULET1) has been designed by the AMULET research group at the Department of Computer Science in the University of Manchester and fabricated by GEC Plessey Semiconductors Limited. The AMULET1 microprocessor was designed using the micropipeline approach based ....

J. A. Brzozowski, C-J. H. Seger, "Asynchronous circuits", Springer-Verlag New York, Inc., 1995.

.... asynchronous, bisimulation, delay dense, delay insensitive, delay extension, isochronic, module, network, semi modular, speed independent 1 Introduction Although much of today s digital design is based on a synchronous approach, there has been a considerable interest in asynchronous circuits [2], more so during the past decade. In contrast to a synchronous circuit, whose operation is under the control of a global clock signal, an asynchronous circuit uses local handshaking between its components. Potential advantages in using asynchronous circuits include lower energy consumption, higher ....

....circuit, whose operation is under the control of a global clock signal, an asynchronous circuit uses local handshaking between its components. Potential advantages in using asynchronous circuits include lower energy consumption, higher speed, and avoidance of clock distribution problems [2]. This research was supported by the Natural Sciences and Engineering Research Council of Canada under grant No. OGP0000871. 1 Among asynchronous designs, the class of so called delay insensitive networks is receiving special attention. Roughly speaking, a network is delay insensitive if it ....

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J. A. Brzozowski and C-J. Seger, Asynchronous Circuits, Springer-Verlag, New York, NY, 1995.

....of P , i.e. t P = t#aP , and we denote by t N the projection of t on the union of the alphabets of the trace structures in N , i.e. t N = t#( Q2N aQ) Note that t P = t fPg . 1 This is only one of many possible behaviors one can associate with a xor gate. It is the unrestricted behavior [BS95] in a single winner model (GSW) assuming inertial delays. 6 The parallel composition of trace structures is a binary operation k such that: i (PkQ) i P [ i Q) Gamma (oP [ oQ) o(PkQ) oP [ oQ; and lg (PkQ) ft 2 (aP [ aQ) j t P 2 lg P t Q 2 lg Qg: The result of parallel ....

....initA 2 st A is the initial state, such that i A and oA are finite and disjoint subsets of U and hst A; edAi is a state graph over i A[oA. Note that branching automata differ from behavior automata only by allowing ambiguous state graphs. Branching automata are similar to the behavior schemas in [BS95], if the choice sets are taken to be the sets of edges with the same label and the same source state. Note that behavior automata are a particular case of branching automata. An example of a branching automaton which is not a behavior automaton is shown in Figure 10 (a) An option of a ....

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J. A. Brzozowski, C-J. H. Seger. Asynchronous Circuits. Springer Verlag, 1995.

....process is illustrated in Section 9. The overall decomposition algorithm is next described in Section 10, and Section 11 concludes the paper. 2 Notions from Ternary Algebra In this section we present for later use some concepts and notation from ternary algebra. For more details see [5]. We use 0 and 1 to denote the usual logic values, and Phi to denote a third value, which will have several interpretations. The uncertainty partial order v on the set f0; Phi; 1g is defined as follows: 0 v 0; Phi v Phi; 1 v 1; 0 v Phi; 1 v Phi; and no other pairs are related by v . The ....

J. A. Brzozowski and C-J. Seger, Asynchronous Circuits, SpringerVerlag, New York, NY, 1995.

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J. Brzozowski and C.-J. Seger. Asynchronous Circuits. Springer, 1995.

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Brzozowski, J. and C.-J. Seger, "Asynchronous Circuits," Springer, 1995.

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BRZOZOWSKI, J., AND SEGER, C.-J. Asynchronous Circuits. Springer, 1995.

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J.A. Brzozowski and C.-J.H. Seger. Asynchronous Circuits. Springer, 1995.

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Brzozowski, J. and C.-J. Seger, "Asynchronous Circuits," Springer, 1995.

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Brzozowski, J. and C.-J. Seger, "Asynchronous Circuits," Springer, 1995.

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J. A. Brzozowski and C.-J. H. Seger, "Asynchronous Circuits," Springer-Verlag, 1995.

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J. A. Brzozowski, C.-J. H. Seger, "Asynchronous Circuits," Springer-Verlag, 1995.

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J. A. Brzozowski and C.-J. H. Seger, "Asynchronous Circuits," Springer-Verlag, 1995.

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J. A. Brzozowski and C.-J. H. Seger, "Asynchronous Circuits," Springer-Verlag, 1995.

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J. Brzozowski and C.-J. H. Seger. Asynchronous Circuits. Springer-Verlag, 1995.

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