J. D. Bruguera and T. Lang. Leading--one prediction with concurrent position correction. IEEE Transactions on Computers, 48(10):1083--1097, 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....this parameter alone cannot address all possible trade offs. The VLSI design community has developed a variety of floating point algorithms, architectures, and pipelining approaches. For example, a 2 path floating point adder [6] was introduced to trade area for latency and other architectures [1, 3, 19] were designed to reduce critical path delay. With modification, these techniques can be applied to FPGAs. To better evaluate the floating point unit design space on FPGAs, we have developed a floating point unit generator which can create a large space of floating point adders, subtractors, ....

....lead to parallel and serial versions of units. 2. The implementation of a variety of well known floating point algorithms can be considered. These include standard 3 stage floating point addition [18] 2 path addition [6] Leading One Detection (LOD) 19] and Leading One Prediction (LOP) [3]. 3. Floating point representations can be customized to use different sign modes for the mantissa and the exponent. Each generated floating point unit can support custom bit width operands. To ease design implementation, our floating point unit generation tool has been integrated into ASC [16] ....

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J. D. Bruguera and T. Lang. Leading--one prediction with concurrent position correction. IEEE Transactions on Computers, 48(10):1083--1097, 1999.

....must be normalized by left shifting the significand by the number of leading zeros. All floating point adders include circuits to either detect or predict the position of the leading non zero digit after the subtraction is performed. The prediction circuits like the work of Bruguera and Lang [2] or the work of Quach and Flynn [16] operate on the adder s operands in parallel with the significand addition. It is to note that in both schemes the original operands are not redundant while the prediction circuits are working on a redundant representation because the prediction is done before ....

....The following example illustrates how leading nonzero digits may be leading insignificant digits. Assuming j l j 15 , Another pattern is 100 00 ve = 011 10 ve. This pattern and its dual ( 1)00 00 ve are what causes a fine adjustment in the case of the previous work [16, 2]. The fine adjustment is basically to indicate that the location of the leading digit should be shifted by one position. We can mentally think of detecting the leading zeros and the leading insignificant digits as the first step followed by a fine adjustment step. In the fine adjustment step if ....

J. D. Bruguera and T. Lang. Leading-one prediction with concurrent position correction. IEEE Transactions on Computers, 48(10):1083--1097, Oct. 1999.

....adder with comparator (adapted from [10] left shift normalization is performed only in the close path, but this path does not include a right shift, so that the comparator delay increases the critical path. For this case, one of the schemes for unknown relative magnitudes should be used and in [2] we consider a generalization of the approach described here. In all the previously reported LOP schemes, there is the possibility of a wrong prediction by one position. The need for this correction is detected late so that the correction increases the critical path. For instance, as shown in ....

....This LOP, that performs the prediction for both positive or negative adder result, uses a concurrent correction scheme based on the checking of the addition carries. That analysis concludes that the LOP in [10] improves the delay time and the hardware complexity by 10 and 45 , respectively. In [2] a detailed comparison for the general LOP case concludes that the solutions using compensation shifter and detection of carries have similar delays. Therefore, our LOP architecture improves both delay time and hardware complexity, with respect to the LOP in [3] 5.4. Floating point adder ....

J.D. Bruguera and T. Lang. Leading--One Prediction with Concurrent Position Correction. Technical Report HPCG--98--008. University of Santiago de Compostela. (1998). Available in http://www.ac.usc.es.

....that the floating point adder uses a LOP to improve the total delay of the addition [5, 14, 16] This way, the coding of the leading one position is done in parallel with the significand adder operation. We assume that the delay of the significand adder is larger than the delay of the LOP [1, 2]. Figure 1b) shows an improved floating point adder architecture [6, 16] It incorporates a comparator and two bit inverters to assure that, in the case of an effective subtraction, the smaller significand is always subtracted from the larger one and a positive result is obtained . The ....

J.D. Bruguera and T. Lang. Leading--One Prediction with Concurrent Position Correction. IEEE Transactions on Computers. Vol. 48. No. 10. pp. 1083--1097. (1999).

....bit of the shifter SHIFTER bit invert. bit invert. add sub. sign A sign B Figure 2: Portion of floating point adder with comparator (adapted from [11] the comparator delay increases the critical path. For this case, one of the schemes for unknown relative magnitudes should be used and in [2] we consider a generalization of the approach described here. In summary, we consider here the common case of a single datapath floating point adder in which a comparison of magnitudes is performed to assure that the output of the adder is positive. In all the previously reported LOP schemes, ....

....This LOP, that performs the prediction for both positive or negative adder result, uses a concurrent correction scheme based on the checking of the addition carries. That analysis concludes that the LOP in [11] improves the delay time and the hardware complexity by 10 and 45 , respectively. In [2] a detailed comparison for the general LOP case concludes that the solutions using compensation shifter and detection of carries have similar delays. Therefore, our LOP architecture improves both delay time Table 3: Gate count of the LOP OUR LOP LOP IN [11] FROM [11] OUR ESTIMATION ELEMENT ....

J.D. Bruguera and T. Lang. Leading--One Prediction with Concurrent Position Correction. Technical Report HPCG--98--002. University of Santiago de Compostela. (1998). (Available in http://www.ac.usc.es in the 1998 reports).

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