John G. Maneatis , "Low-Jitter Process-Independent DLL and PLL Based on self-Bias Techniques" IEEE J. .Solid-State Circuits, vol.31,NO.11 NOV 1996  Home/Search   Document Not in Database   Summary   Related Articles   Check

....2002; revised June 7, 2002. This work was supported by the U. S. Department of Energy under Contract B341491. The authors are with the Computer Systems Laboratory, Stanford University, Stanford, CA 94305 USA (e mail: jaeha stanford.edu) Digital Object Identifier 10.1109 JSSC.2002.803937 [10] [13]. Exploiting the adaptive supply can eliminate or simplify the feedback biasing circuits that are previously required to adjust these parameters. This paper extends the application of adaptive power supply regulation in two ways. First, it explores the design of serial links. Serial links are ....

....which enables simpler schemes such as frequency sweeping and bandwidth widening to aid the frequency acquisition [44] 45] For optimal performance over a wide frequency range, the bandwidth of the PLL and DLL must scale with the operating frequency. Self biased technique proposed in [13] can achieve fixed bandwidth to operating frequency ratio by varying the charge pump current and the feedforward zero properly with the VCO s biasing condition. The same design principle can be applied to the regulated supply PLL and DLL, as demonstrated in [12] In a similar fashion, the local ....

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J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.

..... Jitter can be reduced by decreasing the supply sensitivity of the clock generator. This has been the focus of much research and the result is delay elements with a supply sensitivity that is more than an order of magnitude better than a CMOS inverter [25]. Unfortunately, clock buffers are still generally built with CMOS inverters. Jitter introduced by the clock buffers is a significant limitation to achieving low jitter sampling clocks in a multi channel oversampled receiver because long clock chains are required to drive the large clock loads. ....

....are then described along with techniques to minimize the static phase offsets and jitter caused by these elements. 4.2. 1 Basic Elements The clock generators are implemented with Maneatis style self biased control loops and replica biased, variable delay, differential buffers with symmetric loads [25]. A buffer is shown in Figure 4.2. The two PMOS devices that form the load structures are termed symmetric loads in [23] If the output swing is equal to the bias voltage V bp , then the resistance of the loads is symmetric about the crossing of the differential outputs. This Input[7:0] 0 1 19 ....

J. Maneatis et. al. "Low-jitter process-independent DLL and PLL based on selfbiased techniques," IEEE Journal of Solid State Circuits, vol. 31, no. 11, pp. 17231732, Nov. 1996.

....between them to finely align a clock edge relative to Fig. 12. Digital peripheral loop. the input I O clock [11] The original implementation of this dual loop architecture uses analog differential delay buffers in the core delay line and interpolator with a sophisticated replica biasing scheme [12]. However, the core DLL in this implementation serves a primary role by setting the required voltage of operation while using simple inverters as delay elements. Digital CMOS gates operating off of the regulated voltage can replace the precision analog blocks in the peripheral loop since the ....

J. Maneatis, "Low-jitter process independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 28, Dec. 1993.

....and compromises stability. This bandwidth limitation can be avoided if I CP can compensate for variations in K DL with respect to the reference frequency such that the product of the charge pump current and delay line gain is constant. A self biased differential charge pump design proposed in [30] addresses this variable delay line gain issue, where its charge pump current magnitude is a function of its output control voltage. A design implemented with pMOS differential pairs is presented in Figure 4.11. Similar to the biasing scheme seen in the regulating amplifier, the current for the ....

J.G. Maneatis, "Low-Jitter process independent DLL and PLL based on self-biased techniques," IEEE Journal of Solid-State Circuits, vol. 28, no. 12, Dec. 1993.

....phase offsets. For example, a mismatch in the charge pump could result in non zero net charge when phases are aligned causing the control voltage of the VCO to change; a phase offset would result to compensate. Careful designs correct for these errors with active feedback as shown by Maneatis in [63] who demonstrated a static phase offset of roughly 25ps. Dynamic phase error also poses a significant penalty on the timing margin. The error is often introduced by the jitter in the VCO of the PLL. Although there is a small thermal noise component to jitter, jitter depends primarily on the ....

....technology have large variations. Often, a loop bandwidth that is less than 1 20 f in is used to account for the variations and to ensure stability. Instead, for this design, the zero is implemented as a proportional charge pump current that is summed onto the loop control voltage ( 26] and [63]) depicted in Figure 4.11. The intuition is that the zero applies proportional control in additional to the integral control of the filter capacitor to stabilize the feedback system. After re formulating the expression using proportional currents, the same form as Equation 4.1 can be derived: ....

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J.G. Maneatis, et al., "Low-jitter process-independent DLL and PLL based on selfbiased techniques" IEEE Journal of Solid-State Circuits, Nov. 1996. vol.31, no.11, p. 1723-32

.... the feedback loop of a PLL a lead lag filter is used, implemented by driving the charge pump current to a series resistor capacitor network [1] While many designs have created the needed resistor using the resistance of an amplifier [2] and even made this resistor track the operating frequency [3], all these loops suffer from periodic noise on the control voltage caused by the small ripple current inevitable in most charge pump designs. One alternative to using a resistor is to use a finite impulse response (FIR) filter to generate the needed zero. In this design, the charge pump current ....

J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, Nov. 1996, pp. 17231732.

.... includes both the loop clocks D IN (s) and D REF (s) as well as delay errors introduced by supply or substrate noise D N (s) Each of the two loops is modeled as a single pole system, in which the input, output, and error variables are delays, similarly to the single loop analysis discussed in [66]. For example, the output delay of the core loop D OC (s) in seconds) is the delay established by the core loop delay line, while the input delay D IN (s) is the delay for which the core loop phase detector and charge pump do not generate an error signal. Since the core loop VCDL spans half a ....

....has an inverse square law dependence to the core loop control voltage. This effectively narrows the operating frequency range of the core loop, since the loop bandwidth increases with decreasing operating frequency. To counteract this effect the core loop utilizes the self biasing technique of [66]. As illustrated in Figure 5.7, the current of the core loop charge pump is scaled along with current of the VCDL buffers. Voltage V CN is generated through the replica feedback biasing circuit, while V CP is a buffered version of the charge pump control voltage V CP . In addition to the core ....

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J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723-1732,

....frequency. The data source to each I O transmitter can either be a pseudorandom bit sequence (PRBS) or an externally loaded data pattern. The core DLL generates six differential clocks at 30 phase spacings [23] 24] that are distributed to all the I Os using lowswing differential buffers [25] [26]. In the default operation mode, a clean system clock (cleanClk) is used for clock generation 2 . As mentioned earlier, on start up, the chip undergoes a calibration phase during which the transmitter sends a clock stream along each data line. The data pins are calibrated sequentially using ....

J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.

....to invert the signal after the rightmost buffer) Four differential clocks are available, allowing 8 clocks with a nominal phase spacing of 45 to be generated. The differential delay elements in the VCO (see Figure 2. 6) use replica biased symmetric loads for high supply noise rejection [48]. These loads present a resistance that is symmetric over the signal swing from v cp . The effective load resistance is adjusted to control the RC time constant and thus the delay of the buffer. A replica bias cell adjusts v cn in concert with v cp so that the decreasing resistance of the ....

....as possible, but must remain well below the reference clock frequency for stability. The PLL is self biased so that its loop bandwidth tracks the PLL operating frequency and its damping factor remains constant. This allows the PLL to be optimized for low phase noise over a wide frequency range [48]. To analyze the impact of phase noise on a high speed link, the power spectral density of phase noise can be converted to time domain jitter by integrating phase noise over frequency, or direct time domain analysis of jitter can be performed [57] 58] Empirical data on time domain jitter is also ....

J.G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on SelfBiased Techniques", IEEE Journal of Solid State Circuits, Nov. 1996. vol.31, no.11, p. 1723-32.

.... resistive behavior . Even then transients might slightly saturate the loads and decrease CMRR Hot Interconnects Tutorial Timing 22 A variable load with high CMRR . FET s are non linear but what we really need is to clamp the swing. Also if load transfer function is symmetric CMRR is improved [19] . Use replica feedback biasing to cancel substrate and supply noise Sum of transistor I V and diode connected I V curve I ds V ds V ctrl various V ctrl V bias V ctrl i io o . Replica loop keeps the swing of the buffers equal to Vctrl . In VCO s the replica loop bandwidth should ....

....filt s. We could have static phase offset if I up is not equal to I dn . Does not matter much for a bang bang loop . Can be an important issue in linear PD based loops Current sources with high output impedance (cascoding) Differential charge pumps [23] Replica feedback biased charge pumps [19] up dn I dn I up C FILT Hot Interconnects Tutorial Timing 29 Typical 2nd 3d order PLL filter For a VCO based PLL, insert a resistor in series with integrating C. Explicit C 2 is often used to suppress ripple. Implement resistor in high resistivity layer (poly, diffusion, well) ....

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J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques", JSSC, Nov. 1996

....this overlap is easily obtainable. 4. VARIABLE LENGTH VCO The VCO, shown in Fig. 5, is comprised of 16 delay cells and a multiplexer which dynamically selects the appropriate length. To reduce jitter, a differential pair was selected due to its low sensitivity to power supply and substrate noise [10,11]. The delay cell contains a source coupled pair with PMOS diodes used for clamping the output voltage to provide a fixed common mode and swing without the need for a replica bias circuit [10] The function of the multiplexer is to select the desired differential signal and convert it into a ....

F. G. Maneatis, "Low-jitter process-independent DLL and PLL based of self-biased techniques," IEEE Journal of Solid-State Circuits, vol. 31, no.11, November 1996.

....skew. Delay is adjusted by varying the supply voltage with a linear voltage regulator. A source coupled differential pair with replica bias delay adjustment is widely used as a delay element due to its low supply sensitivity of 0. 2 (fraction delay change per fraction of supply change) 11] [12]. However, compared to a static CMOS inverter delay element, it requires more power and is more susceptible to substrate noise and transistor mismatches. The power consumed in an N phase differential inverter delay line and differential source coupled delay line are inverter element based ....

....is increased) power saving is more significant. Inverter delay elements are also more robust against substrate noise and transistor mismatches. A source coupled delay element is particularly vulnerable to any noise introduced to its tail current source. For the delay element described in [12], it was found that the sensitivity of its delay to the tail current around the correct bias point is about 0.5. Using this relationship, we can derive the variation in delay as where [16] The last approximation is valid in this case since the tail current source has a small . Static mismatches ....

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J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.

....oscillator (or a delay line with its phase input locked to its output phase) and tap the output of each of its stages. For example, a 6 stage oscillator employing differential stages, can generates 12 edges evenly spaced in the 0 360 o interval. An example of a robust differential delay element [26] with low supply sensitivity is shown in Figure 12. For even finer phase spacing than a single buffer delay, phase interpolators can be used to generate a clock edge occurring halfway between two input phases. The design of an interpolator uses two buffers each with different phases as inputs ....

....the 8 FO 4 clock. Jitter and phase error should also scale with technology, if certain constraints are met. The supply substrate sensitivity of a buffer is typically a constant percentage of its delay on the order of 0.1 0. 3 delay supply for differential designs with replica feedback biasing [26]. This implies that the supply and substrate induced jitter on a DLL scales with operating frequency the shorter delay in the chain, the smaller the phase noise. This argument also holds for the jitter caused by the buffer chain that follows the DLL. As technology scales, the delay of the ....

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Maneatis, J.G. et al. "Low-jitter process-independent DLL and PLL based on self-biased techniques" IEEE Journal of Solid-State Circuits, Nov. 1996. vol.31, no.11, p. 1723-32

....the integrated PLL offers the advantage of high speed, low power and low cost. Because of the increased interest in high performance fully integrated CMOS PLLs,low phase noise voltage controlled oscillator(VCO) as one of its most important building blocks, has become an active area for research [1, 2, 3, 4, 5, 6]. Ring oscillators, with their ease of integration and large tuning range, are promising candidates for the implementation of monolithic CMOS PLLs. This paper attempts to determine the best delay cell topology for ring oscillators. The methodology has been to design a number of oscillators (five) ....

....contribution to this work. M2 M4 M5 M8 M9 M11 Vin M10 M6 VinM1 M3 Vout VoutM7 Ib Figure 1: Differential inverter with Maneatis loads M2 M6 M7 M9 Vin M8 VinM1 M3 M4 M5 Vout Vout Ib Figure 2: Differential inverter with single PMOS loads PMOS loads (Maneatis loads) [1]. M4 ; M7 are equally sized and provide a more linear I V characteristic than a single device load [1] The delay stage is biased by devices M8 M11, and the delay time is controlled by the bias current I b . Alternately, the load M4 ; M7 of the delay stage can be implemented as a single ....

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J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE JSSC, vol. 31, pp. 1723--1732, Nov 1996.

....but if the two are out of phase, the bias voltages increase or decrease to speed up or slow down the VCDL accordingly. Replica biasing is used to insure that the DLL will work over all process corners. The delay elements, replica bias circuits and charge pumps are all based on published designs [20], 21] and their operations will be described in Sections 4.1, 4.2, and 4.3. We will go into considerably more depth in describing the design of phase frequency detectors for DLLs in Section 4.4. There are some design issues that we will explore that are not adequately discussed in the ....

....adjusted dynamically by the feedback portion of the loop. Figure 4.2: Delay elements. A differential structure with symmetric loads. Delay is controlled by adjusting V nbias and V pbias . The delay elements use a differential structure, as shown in Fig. 4. 2, in order to increase noise rejection [20]. The input devices M2 and M3 are a differential pair which steer the current through each branch. The analog voltage V nbias on M1 helps determine the delay through the delay element by controlling the total 16 current through each branch. Devices M4 M7 make up the two symmetric load elements ....

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J. Maneatis. Low-jitter process-independent DLL and PLL based on self-biased techniques. IEEE Journal of Solid-State Circuits, 31(11):1723--1732, Nov. 1996.

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J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.

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J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," in ISSCC 1996.

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John G. Maneatis , "Low-Jitter Process-Independent DLL and PLL Based on self-Bias Techniques" IEEE J. .Solid-State Circuits, vol.31,NO.11 NOV 1996

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John Maneatis, "Low-Jitter Process Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1723-1782, 1996.

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John Maneatis. Low-Jitter Process Independent DLL and PLL Based on Self-Biased Techniques. IEEE Journal of Solid-State Circuits, 31(11), November 1996.

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J. Maneatis, "Low-jitter process independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.

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J.G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.

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J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723--1732, Nov. 1996.

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Maneatis, J., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques", IEEE Journal on SolidState Circuits, Vol. 31, No. 11, November 1996, pp. 1723-1732.

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J.G. Maneatis et al., "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE J. Solid-State Circuits, Vol. 31, No. 11, Nov. 1996, pp. 1,723-1,732.

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