Robert C. Frye. Balancing performance and cost in cmos-based thin film multichip module. In Proceedings of IEEE Multi-Chip Module Conference, pages 6--11, 1993. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Optimal Sizing of High Speed Clock Networks Based on.. - Zhu, Dai, Xi (1993) (8 citations) (Correct)
....on the wire width in 1m for the IC chip and the wire width in 10m for the MCM. Based on these typical values and formulae shown in (3.1) and (3.2) in Section 3:2, we can derive the modeling of a clock branch with a given length and width. In (3. 2) h is taken 15m based on a advanced MCM design [12]. Note that terminals in IC chip examples have two different loading capacitances. Figure 6.2 shows the plots of skew improvement when our optimal sizing method is applied on the Example 1 which has loops and Example 3. Example 2 is not illustrated here and it shows a similar skew improvement to ....
Robert C. Frye. Balancing performance and cost in cmos-based thin film multichip module. In Proceedings of IEEE Multi-Chip Module Conference, pages 6--11, 1993.
High-Performance Bit-Serial Datapath Implementation for.. - Isshiki (1996) (1 citation) (Correct)
....(thus called a silicon on silicon MCM) which has the highest wiring density of all and various efforts have been made in lowering the cost of this technology. AT T Bell Laboratories have being developing the MCM D technology which targets high volume consumer products in the telephone business [40]. In their MCM D process, the substrate contains two metal layers that are used as interconnect or as passive components such as resistors and capacitors [41] Conventional ICs, sometimes postprocessed to meet solder assembly requirements, are diced, bumped, and tested. They are then attached, ....
....second level package, used for insertion into the final system, is typically a pin or ball grid array (BGA) There are two layers with a wire pitch on the order of 1.5 mils. The process has also been carefully optimized to minimize the cost without sacrificing the performance of digital circuits [40]. 2.3.2 Impact of MCM Technology on FPGA based System The advantages of MCM over conventional single chip packaging are well known: smaller feature size, lower electrical parasitics due to chip interconnections, increased interconnect resources, and reduced packaging cost. Also, the new issues ....
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Robert C. Frye, "Balancing Performance and Cost in CMOS-Based Thin Film Multichip Module," Proc. IEEE Multichip Module Conference, pp. 6-11, 1993.
A Field Programmable Multi-chip Module (FPMCM) - Joel Darnauer (1994) (6 citations) (Correct)
....sectional view of a typical MCM assembly. Key features of the AT T process that make it suitable for FPMCM are flip chip die attach and high performance, high density interconnect. The process has been carefully optimized to minimize cost without sacrificing the performance of digital circuits [Fry93] 1.2 Advantages of MCM MCMs have many advantages over traditional packaging: lower electrical parasitics between packages, smaller size, increased interconnect resources, and reduced packaging cost. The MCM packaging technology can provide value to a system producer in two ways: by providing ....
....Consumption Lower capacitive loads of shorter MCM interconnections provide substantial power savings. The power used by MCMs is typically about fifty percent of conventional packaging. This power savings increases dramatically when the drivers are specifically designed for the MCM interconnects [Fry93] Low power is an important feature of MCMs for several reasons. Most important is that the power density in an MCM can quickly exceed the ability of most materials to carry heat away from components, resulting in decreased reliability and lifetime. Secondly, components that have large transient ....
Robert C. Frye. Balancing performance and cost in cmos-based thin film multichip modules. In IEEE Multichip Module Conference, pages 6--11, 1993.
Field-Programmable Multi-Chip Module (FPMCM) for.. - Isshiki, Dai (1994) (Correct)
....to be very dense. And since the parasitic capacitance is significantly lower compared to on board communications, fast drivers can be built in the die. AT T Bell Laboratory has designed a set of low voltage, high speed IO buffers optimized specifically for MCM which can operate at up to 400MHz [10]. 2.3 FPMCM I Architecture We have designed and fabricated the first generation FPMCM (FPMCM I) 7] 8] and the board for testing the assembled modules and also running various applications is being developed. The purpose of the first generation device is to fully exercise the MCM fabrication ....
Robert C. Frye, "Balancing Performance and Cost in CMOS-Based Thin Film Multichip Module," Proc. IEEE Multichip Module Conference, pp.6-11, 1993.
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