Gajski,D., Kuhn,R.H., "Guest Editors Introduction New VLSI Tools", IEEE Computer, vol. 16, #2, 1983, pp. 14-17  Home/Search   Document Not in Database   Summary   Related Articles   Check

....I, pp. 55 58, Vsters, Sweden, Aug. 25 27, 1998. 2] J. berg, A. Jantsch, A. Hemani, Validation of Interface Protocols Using Grammar based Models , In the Proc. of the IEEE International High Level Design Validation and Test Workshop (HLDVT 98) pp. 40 46, La Jolla, California, Nov. 12 14, 1998. [3] J. berg, P. Ellervee, A. Hemani, Grammar based Modelling of Clock Protocols for Low Power Implementation: A Case Study , In Proc. of NorChip 98, pp. 144 153, Lund, Sweden, Nov. 9 10, 1998. 4] A. Jantsch, J. berg, A. Hemani, Is there a Niche for a General Purpose Protocol Processor , In Proc. ....

....be able to develop tools for design automation it is important to have conceptual models of the different domains and levels of descriptions if the designs we re trying to model. In 1983, Gajski and Kuhn introduced the Y chart for describing the taxonomy of design automation in electronic systems [3, 4]. It has proven to be a very valuable reference point and is up to today the most commonly used method for taxonomy of electronic systems. The Y chart is shown in Figure 1.1. Effort spent in developing a 20kGates design at various design steps over the years. Modified from [2] 40 60 70 30 50 ....

D. D. Gajski, R. Kuhn, "Guest Editors' Introduction: New VLSI Tools", IEEE Computer, vol. 16, no. 12, pp. 11-14, Dec. 1983.

....in silicon. Following a formal methodology, defined as a set of models and a set of transformation between the models, the design is gradually refined to lower and lower levels of abstraction. As depicted by the Y Chart (Figure 1) four general layers of abstraction are commonly distinguished [1]: a) System level (b) Register transfer level (RTL) c) Gate level (d) Transistor level With lower levels, the design process focuses on more and more detailed aspects of the system. At each level, the designer works with a specific set of objects. Objects at higher levels of abstraction are ....

....of the required width (line 56 and line 57) The PEs then connect to the wires through their ports (lines 2 7 and lines 28 34) Depending on the access direction, PEs connect to the reader and or writer side of the bit vectors and signal channels. Reader interface interface ISignal f bit [1] val(void ) get current value void waitval ( bit [1] v) wait for value Writer interface interface OSignal f void assign ( bit [1] v) drive signal Channel implementation channel CSignal ( implements ISignal , OSignal f bit [1] value ; 15 event e; void assign ( bit [1] ....

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D. D. Gajski, R. Kuhn. "Guest editors introduction - New VLSI tools." IEEE Computer, pp. 11-14, 1983.

....design methodologies rely on a stepwise re nement ow to map a circuit speci cation onto a mask layout for fabrication. Within this ow, the circuit description is transformed and manipulated on di erent levels of abstraction. We generally distinguish between the following levels of abstraction (Gajski and Kuhn, 1983): 1. On system level the system is described in terms of a set of hardware, software and memory components and interacting algorithms they perform to provide a certain functionality. 2. On behavioral or architectural level the individual components (ASICs, datapaths, software processes) are ....

Gajski, D. and Kuhn, R., Guest Editors' Introduction: New VLSI Tools, IEEE Computer , 6 , 11-14, 1983.

....and system level, one can find mainly approaches targeting energy minimization. 2.1.3 DESIGN ABSTRACTION LEVELS Digital systems can be specified at different levels of abstraction. A now traditional view of these levels and the relations between them is captured by the Y chart, introduced in [Gaj83]. We will only briefly present the different levels, to form a point of view which is relevant for the work described in this thesis. The most commonly used levels of abstraction are the physical, the logic, the register transfer (RT) the behavioral, and the system level (Figure 2.3) At system ....

Gajski, D.D.; Kuhn, R., "Guest Editors' Introduction: New VLSI Tools," IEEE Computer, vol. 6, no. 12, December 1983, pp 11-14. 99

.... its specification [1, 2, 3] It is desirable, that the implementation description and the specifications are at different abstraction levels or within different domains (behavioural, structural, or physical) in order to enforce an incremental design philosophy used in designing complex circuits [4, 5]. The problems that accompany formal verification within such a context are [6] ffl the inherent complexity of modeling large systems, ffl the complexity of related proofs, ffl the difficulty of modeling an object in the physical world, and ffl the difficulty of formally representing the ....

D. Gajski and R. Kuhn. Guest editors' introduction: New VLSI tools. Computer, 16(12):11--14, December 1983.

....used in retargeting the state machines are given in Section 3. Section 4 highlights the results obtained. 2.0 The Retargeting Process Retargeting is a technologically complex process that cannot be done without using specialized tools. We will use the notation introduced by Gajski and Kuhn [5] and Figure 1 to describe the retargeting procedure in terms of design synthesis [7] The Y chart depicts how each element in a system can be described in behavioural, structural and physical domain. The level of abstraction increases when going from the center point, and mappings between the ....

Gajski, D. and Kuhn, R., Guest Editors' Introduction: New VLSI Tools, IEEE Computer, Vol. 6, No. 12, pp. 11-14, Dec. 1983.

....components. The result is the system architecture of PEs connected via busses. From there on, each of the PEs is then further implemented through software and hardware synthesis. 1. 2 Traditional Models There are several approaches dealing with classification and structuring of the design process [3, 8, 9]. However, none of these defines an actual flow with models at specific points. Traditionally, abstracted models of a system design are used mainly for simulation purposes. In such simulationcentric approaches, the designer is responsible for manually rewriting the model at a fixed level of ....

....and computational units of hierarchy can only be composed in a parallel fashion, i.e. all blocks are active all the time and it is cumbersome to describe a sequential composition of computation. 2. ABSTRACTION LEVELS A general classification of the design process is available through the Y Chart [3]. It defines system, register transfer (RT) gate, and transistor levels where each level is defined by the type of objects and where higher level objects are hierarchically composed out of lower level ones. At each level, Specification Architecture Computation synthesis Communication Behavior ....

D. D. Gajski and R. Kuhn. Guest editors introduction: New VLSI tools. IEEE Computer, pages 11--14, 1983.

....Constraints MOCs Component implementation (HW SW synthesis) Figure 1: System design tasks. each of the PEs is then further implemented through software and hardware synthesis. 1. 2 Traditional Models There are several approaches dealing with classification and structuring of the design process [1, 2, 3]. However, none of these defines an actual flow with models at specific points. Traditionally, abstracted models of a design are used mainly for simulation purposes. In such simulationcentric approaches, the designer is responsible for manually rewriting the model at a fixed level of abstraction ....

....i.e. all blocks are active all the time. Transistor level Gate level Register transfer level (RTL) System level Behavioral Structural Physical Figure 2: Y Chart. 2 Abstraction Levels A general classification of the design process is available through the Y Chart as shown in Figure 2 [1]. It defines system, register transfer (RT) gate, and transistor levels where each level is defined by the type of objects and where higher level objects are hierarchically composed out of lower level ones. At each level, the design can be described in the form of a behavioral, a structural ....

D. D. Gajski, R. Kuhn. "Guest editors introduction - New VLSI tools." IEEE Computer, pp. 11-14, 1983.

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Gajski,D., Kuhn,R.H., "Guest Editors Introduction New VLSI Tools", IEEE Computer, vol. 16, #2, 1983, pp. 14-17

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