D. Niehaus, E. Nahum, and J. Stankovic. Predictable Real-Time Caching in the Spring System. In Proceedings of the Eighth IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87. May 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....level of machine code [28] Only Harmon s tool took the impact of instruction caches into account for restrictive circumstances, i.e. only for small code segments that entirely fit into cache. Niehaus outlined how the effects of caching can be taken into account in the prediction of execution time [53]. He suggested that caches be flushed on context switches to provide a consistent cache state at the beginning of each task execution. He provided a rough estimate of the benefit of caches for speedup and tried to determine the percentage of instruction cache references that can be predicted as ....

....instruction caching and was only able to analyze small code segments that contained no function calls and entirely fit into cache. Thus, this tool was able to assume that at most one miss will occur for each reference. Niehaus outlined how the effects of caching on execution time can be estimated [53], as discussed in the last chapter. However, no general method was provided to analyze the call graph of a program and the control flow within each function. Lin and Liou suggested that more frequently executed tasks be placed entirely in cache and other tasks be denied any cache access [44] ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable real-time caching in the spring system. In IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87, 1991.

....references [1 3, 6 9, 11 13, 19, 23] discuss techniques for analyzing cache performance. Pipeline analysis for real time predictability has been reported in [4, 5, 10, 22, 24] To our knowledge, the only other paper to consider the relationships between programming and analysis techniques is [15]. 8. Acknowledgments We thank the referees for prompting us to refine the discussion of pipeline issues in Section 5, and for alerting us to similarities with the work of others. We thank Microware Systems Corporation for their support of this project. We are also grateful to the Institute of ....

D. Niehaus, E. Nahum and J. Stankovic, Predictable Real-Time Caching in the Spring System, Proceedings of the Eighth IEEE Workshop on RealTime Operating Systems and Software, 1991, 80-87.

....level of machine code [6] Only Harmon s tool took the impact of instruction caches into account for restrictive circumstances, i.e. only for small code segments which entirely fit into cache. Niehaus outlined how the effects of caching can be taken into account in the prediction of execution time [17]. He suggested that caches be flushed on context switches to provide a consistent cache state at the beginning of each task execution. He provided a rough estimate of the benefit of caches for speedup and tried to determine the percentage of instruction cache references which can be predicted as ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable real-time caching in the spring system. In IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87, 1991.

....types of cache misses cannot be avoided if the cache has a limited size and or set associativity. Among the analytical WCET prediction schemes that we are aware of, only three schemes take into account the timing variation resulting from intra task cache interference (two for instruction caches [19, 21] and one for data caches [24] The static cache simulation approach which statically predicts hits or misses of instruction references is due to Mueller, Whalley and Harmon [19] In this approach, instructions are classified into the following four categories based on a data flow analysis: ffl ....

....n1 Theta n2 references to b j are treated as cache misses in this approach. Another limitation of this approach is that the approach has not addressed the issues of locating the worst case execution path and of calculating the WCET, which are critical in scheduling tasks in real time systems. In [21], Niehaus et al. discuss the potential benefits of identifying instruction references corresponding to alwayshit and first miss in the static cache simulation approach. However, as it is noted in [19] their analysis is rather abstract and no general method to analyze the worst case timing ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable Real-Time Caching in the Spring System. In Proceedings of the 8th Workshop on RealTime Operating Systems and Software, pages 76-- 80, 1991.

....used to obtain such bounds. Measurement based techniques are, in many cases, inadequate to produce a timing estimation for real time systems since their predictions are usually not guaranteed, or enormous cost is needed. Due to these limitations, analytical approaches are becoming more popular [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]. Many of these analytical studies, however, consider a simple machine model, thus largely ignoring the timing effects of pipelined execution and cache memory [8, 12, 13, 15] A. Timing Analysis of Pipelined Execution The timing effects of pipelined execution have been recently studied by Harmon, ....

....types of cache miss cannot be avoided if the cache has a limited size and or set associativity. Among the analytical WCET prediction schemes that we are aware of, only four schemes take into account the timing variation resulting from intra task cache interference (three for instruction caches [10, 9, 7] and one for data caches [14] The static cache simulation approach which statically predicts hits or misses of instruction references is due to Arnold, Mueller, Whalley and Harmon [10] In this approach, instructions are classified into the following four categories based on a data flow ....

[Article contains additional citation context not shown here]

D. Niehaus, E. Nahum, and J. A. Stankovic, "Predictable Real-Time Caching in the Spring System," in Proceedings of the 8th Workshop on Real-Time Operating Systems and Software, pp. 76--80, 1991.

....number of CPU (or coprocessor) cycles taken for executing every instruction, the efficiency of the prefetch queue and of the cache, and the number of wait states when accessing the bus for memory or I O operations. All these factors must be considered in a software model of the whole architecture [6] [1] 5 The Tool The model we are using includes the simulation of the processor in a table driven fashion, where assembly instructions are translated into execution times depending on their operating code, operands and addressing mode. At the moment, we assume that all other components of the ....

D. Niehaus, E. Nahum and J. A. Stankovic "Predictable Real-Time Caching in the Spring System", IFAC Real-Time Programming, 79-83, 1991.

....attracted some attention: Li et al. 6] analyze the cache interference within a single task. A genuine approach to estimate worst case penalty in the presence of multiple tasks is to preschedule all context switches and consider the cache to be in a worst case state after a switch. Niehaus et al. [11] propose this approach for the Spring real time system. Our work addresses a more open environment where not all context switches can be prescheduled. Kirk [5] describes SMART, Strategic Memory Allocation for Real Time. Essentially, he proposes to use extra information for the cache line mapping ....

D. Niehaus, E. Nahum, and J. A. Stnakovic. Predictable real-time caching in the Spring system. In IFAC Systems and Software Workshop, Atlanta, 1991.

....unattractive in non real time systems, real time designers worried about WCET view it as a significant improvement. This article analyzes two fundamental methods of managing caches for predictable behavior. The two methods are software based and have been presented previously in the literature [12, 9]. We quantitatively compare the policies by leveraging an existing analytical cache model in a novel manner that allows exploration of system performance across a wide range of designs. Although currently limited to systems with a single level of cache, this analysis reveals that cache policy ....

....can occur. Kirk and Strosnider [6] detail a hardware design for the MIPS R3000 that allows a cache to be partitioned among processes. Mueller [9] implemented a compiler that partitions the cache strictly through software, via positioning of code. On the other hand, the Spring Real Time System [12] controls where context switches can occur using a software technique that defines regions of code during which interrupts are masked. By assuming the cache is empty upon entry into one of these regions, techniques can determine the WCET cache behavior between the entry and exit points because the ....

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D. Niehaus, E. Nahum, and J.A. Stankovic. Predictable Real-Time Caching in the Spring System. IFAC Real-Time Programming, pages 79--83, 1992.

....(object code) since the experimental system only had an instruction cache. Yet, he did not discuss the opportunities for compiler transformations of code or data. An alternative to cache partitioning for preemptive systems is provided by the non preemptive scheduling paradigm of the Spring system [NNS91]. Under the Spring system, the execution of a task between two scheduling synchronization points cannot be interrupted. Thus, the caching behavior between these points can be predicted. 4 Caches are assumed to be flushed during context switches, which provides predictability but does not improve ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable real-time caching in the spring system. In IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87, 1991.

....it is not an exact analysis (i.e. it is sufficient but not necessary) It converges to 0.69 (i.e. ln(2) as the number of tasks approaches infinity. However, for a randomly chosen large task set the likely bound is 88 percent [38] Another time domain technique is presented in the Spring system [31], where tasks execute without preemptions, thus avoiding the extrinsic interference from its roots. 2.3 Cache partitioning Cache partitioning (abbreviated PART) is aimed at improving the cache predictability by annulling the extrinsic interference by providing each task with a private cache ....

D.Niehaus, E.Nahum and J.A.Stankovic. "Predictable Real-Time Caching in the Spring System". Workshop on Systems and Software, Atlanta, 1991.

....level of machine code [6] Only Harmon s tool took the impact of instruction caches into account for restrictive circumstances, i.e. only for small code segments which entirely fit into cache. Niehaus outlined how the effects of caching can be taken into account in the prediction of execution time [17]. He suggested that caches be flushed on context switches to provide a consistent cache state at the beginning of each task execution. He provided a rough estimate of the benefit of caches for speedup and tried to determine the percentage of instruction cache references which can be predicted as ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable real-time caching in the spring system. In IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87, 1991.

No context found.

D. Niehaus, E. Nahum, and J. Stankovic. Predictable Real-Time Caching in the Spring System. In Proceedings of the Eighth IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87. May 1991.

....would be present in target hardware that contained instruction or data caches, which the current Spring node does not. Calculating at least a portion of the effects of instruction caches on the worst case behavior of a procedure is a non trivial problem, but can be done under some circumstances [4]. The memory access time is ultimately determined by the location within the memory 5 hierarchy of the data structure being accessed relative to that of the process accessing it. Knowledge of the node architecture is only a part of the information required to determine memory access time, but ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable Real-Time Caching in the Spring System. In Proceedings of the Eighth IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87. IEEE, May 1991.

....significantly from other efforts. This paper presents the basic translation method, and gives examples of how it treats programming language constructs used to specify critical sections and synchronous communication. We address other aspects of constructing a predictable real time system elsewhere [11, 9]. One of our goals is to establish a source language, Spring C, that can serve as a target for many of the existing languages. The details of the language we have developed for describing the process properties and system configuration, and our modifications to C syntax are described in [10] The ....

....and the code that is calling them. This will enable us to predict a substantially smaller WCET if loops containing subroutine calls can coexist in the cache with the code of the subroutines they call. A preliminary discussion of how we handle the effects of instruction caching is given in [11]. Symbolic expressions are produced by subgraph reductions that construct expressions for the execution time instead of merely accumulating numerical values. This will make it possible to construct expressions for the WCET of a task, which could depend on the number of input data items or on the ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable Real-Time Caching in the Spring System. In Proceedings of the Eighth IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87. IEEE, May 1991.

....adding a cache and pipeline to where the machines seems to be fast enough is not the correct approach. Rather, one needs to either increase the speed of the simple machine by new technology, use parallelism afforded by multiple machines, or use what we will call here predictable real time caching [9]. Other examples of the type of support needed for the application processor are: shift instructions should be implemented as a barrel shifter so that any number of bits (up to some predetermined number) can be shifted in a single cycle; all instructions should be the same size; support is ....

D. Niehaus, E. Nahum, and J. A. Stankovic. Predictable Real-Time Caching in the Spring System. In Proceedings of the Eighth IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87. IEEE, May 1991.

....with the existing hardware were discovered. Creating a solution lead to the formulation of more general results addressing synchronization in multiprocessor real time systems [53] The design of the Spring system makes it possible to consider predicting the effects of caching on the WCET of a task [59]. The viability of the approach depends on the fact that under Spring application tasks are shielded from external interrupts, and are not subject to preemption at arbitrary times [87] The explicit execution plan construction ensures that a task will complete without interruption, and analysis of ....

....would also be created by instruction and data caches, which the current Spring target architecture does not possess. Calculating at least a portion of an instruction cache s effects on the worst case behavior of a procedure is a non trivial problem, but can be done under some circumstances[59]. This issue is relevant, since the next target architecture for Spring will almost certainly have instruction and data caches, which must be used predictably, if they are to be used at all. The NUMA hierarchy is of considerable interest during compilation, since the time for a memory access is ....

[Article contains additional citation context not shown here]

Niehaus, D., Nahum, E., and Stankovic, J. A. Predictable Real-Time Caching in the Spring System. In Proceedings of the Eighth IEEE Workshop on Real-Time Operating Systems and Software, pages 80--87. IEEE, May 1991.

No context found.

Niehaus, D., J. A. Stankovic, and E. Nahum, "Predictable Real-Time Caching in the Spring System," IEEE Real-Time Systems Newsletter, vol. 7, no. 4, pp. 75-79, Fall 1991.

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