D. B. Kirk. SMART (strategic memory allocation for realtime) cache design. In Proceedings of 10th Real-Time Systems Symposium (RTSS'89), Dec. 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....a tight and safe way, with an acceptable loss of performance. Combined with a timing analysis platform, we may estimate the WCET much tighter than previous approaches. Furthermore, it can be used for computing WCET estimates in multi task systems when combined with the cache partitioning technique [19]. Overall, this paper contributes with a unique technique that provides a considerable step toward a useful worst case execution time prediction of actual architectures. Written as a compiler pass, it both issues lock unlock load instructions and computes the worst case memory performance in ....

D.B. Kirk. SMART (strategic memory allocation for real-time) cache design. In 10th Real-Time Systems Symposium, Dec. 1989. 19

....and safe way, with an acceptable loss of performance. Combined with a timing analysis platform, we may obtain a much tighter WCET estimate than previous approaches. Furthermore, it can be used for computing WCET estimates in multi task systems when combined with the cache partitioning technique [18]. Overall, this paper contributes with a unique technique that provides a considerable step toward a useful worst case execution time prediction of actual architectures. Written as a compiler pass, it both issues lock unlock load instructions and computes the worst case memory performance in ....

D. Kirk. SMART (strategic memory allocation for real-time) cache design. In Proceedings of 10th Real-Time Systems Symposium (RTSS'89), Dec. 1989.

....This cache related pre emption delay (CRPD) or cache refill penalty that can be considered as an indirect cost is illustrated in figure 1 and 8. The CRPD can be eliminated or reduced by partitioning the cache so each task has a private part of it, but to the price of decreased over all performance[12, 13, 14]. Continuously measuring cache performance. By continously monitoring the cache miss ratio, maximum and average miss ratio during a time slice can be determined. If the time slice is smaller than T 1 T 2 without pre emption T 1 T2 preempts T1 T1 cont. Cache refill penalty = CRPD with ....

David B. Kirk. SMART (strategic memory allocation for real-time) cache design. In IEEE Computer Society Press, editor, Proceedings of the Real-Time Systems Symposium - 1989.

....as to control persistence and eliminate interference. Allowing this separation has the knock on effect of improving the predictability and determinism of the cache. The idea of exposing the cache to the programmer has been proposed before [19] and has been investigated by Juan et al. 10] Kirk [11] Jain et al. 9] and Mueller [16] The most obvious deficiency of most these systems, is the inflexible manner in which cache partitions are allocated and the questionable approach of using entirely hardware or software based designs. These techniques lack interaction from the one component, the ....

D.B. Kirk. SMART (Strategic Memory Allocation for Real-Time) Cache Design. In IEEE Symposium on Real-Time Systems, pages 229--237, December 1989.

....after a preemption. Cache partitioning and cache locking. A second class of approaches to deal with caches in real time systems is to use them in a restricted or customized manner, so as to adapt them to the needs of real time systems and schedulability analysis. Cache partitioning techniques [8, 5, 14] assign reserved portions of the cache (partitions) to certain tasks in order to guarantee that their most recently used code or data will remain in the cache while the processor executes other tasks. The dynamic behavior of the cache is kept within partitions. These techniques eliminate the ....

D. B. Kirk. Smart (strategic memory allocation for realtime) cache design. In Proceedings of the 10th IEEE RealTime Systems Symposium (RTSS89), pages 229--237, Santa Monica, California, USA, Dec. 1989.

....preemption. Task partitioning and cache locking. A second class of approaches to deal with caches in real time systems is to use them in a restricted or customized manner, so as to adapt them to the needs of hard real time systems and schedulability analysis. Cache partitioning techniques (e.g. Kir89, SS93] assign reserved portions of the cache (partitions) to certain tasks in order to guarantee that their most recently used code or data will remain in the cache despite preemptions. The dynamic behavior of the cache is kept within partitions. These techniques eliminate the inter task ....

D. B. Kirk. Smart (strategic memory allocation for real-time) cache design. In Proceedings of the 10th IEEE Real-Time Systems Symposium (RTSS89), pages 229--237, Santa Monica, California, USA, December 1989.

....data code whichwas present in the cache This work is supported in part byagrant from NSF (MIP9708067) Research at UCI is supported by JSPS postdoctoral fellowships for research abroad. but is displaced from the cache by the other tasks. One approachtoavoid CRPD is cache partitioning [5, 15]. In this approach, the cache is divided into several disjoint partitions each of which is dedicated to a speci c task. Although cache partitioning makes it easier to analyze cache behavior in a preemptivemultitask environment, it causes serious degradation of cache performance (therefore, ....

D. B. Kirk, \SMART (strategic memory allocation for real-time) cache design," In ##### ## ######### ####### #####, pp. 97-108, 1989.

....cache contents will be more or less displaced by the new running task. This performance loss is also called cache related pre emption delay (CRPD) To eliminate the CRPD and extrinsic cache effects, Kirk suggests to partition the cache into segments and assign task their own segment of the cache [2]. This can also be accomplished in software by locating code and data so they won t map and compete for the same areas in the cache [3] Both these problems must be solved or correctly analyzed to be able to give an accurate and tight Worst Case Execution Time (WCET) The WCET is the base to all ....

David B. Kirk. SMART (strategic memory allocation for real-time) cache design. In IEEE Computer Society Press, editor, Proceedings of the Real-Time Systems Symposium - 1989, pages 229--239, Santa Monica, California, USA, December 1989. IEEE Computer Society Press.

....grows, the predictions and actual execution times differ significantly. Another approach to the data cache problem focuses on active management of the cache. If we can prevent the invalidation of the cache content, then execution time is predictable. One option is to partition the cache [14, 20] so that one or more partitions of the cache are dedicated to each real time task. This approach helps the analysis of the cache access time since the influence of multitasking is eliminated, but on the other hand, partitioning limits the system s performance [21] Techniques exist to take into ....

D. Kirk. SMART (Strategic Memory Allocation for Real-Time) cache design. In Proc. 10th IEEE Real-Time Systems Symp., pages 229--239, Santa Monica, California, December 1989. IEEE.

....points [12] or are restricted to a fixed order of tasks and try to find an optimal order [8, 15] It is not possible to combine these approaches with commonly used real time operating systems. Other approaches restrict the abilities of microarchitectural features, e.g. by cache partitioning [9]. There is also work that incorporates cache behaviour into fixed priority schedulability analysis for preemptive systems [2, 4, 11] However, all these approaches consider cache related preemption costs isolated from pipeline effects (if pipeline effects are considered at all) Basumallick and ....

D. B. Kirk. Smart (strategic memory allocation for realtime) cache design. In Proceedings of the 10th Real-Time Systems Symposium, pages 229--237, Dec. 1989.

....the average memory access cost. Unfortunately the temporal characteristics of caches are dependent upon memory access patters which are difficult, if not impossible, to predetermine. This becomes even more complex if multiple tasks execute concurrently, unless each task has its own area of cache [5]. Another technique is to perform loads and stores concurrently with executing other instructions. However, data dependencies severely limit the latency which may be tolerated. 3.3 Latency and frequency tradeoffs In order to exploit latency and frequency tradeoffs an application needs to be ....

D.B. Kirk. SMART (Strategic Memory Allocation for Real-Time) cache design. In 10th annual real-time system symposium, pages 229--237, 1989.

.... Examples include the design of HARTS [Shi91] based on interconnecting off the shelf components) the MAFT [McE88] design (where the concern is failure resilience and scheduling) MAX [R 87] which is a loosely coupled multicomputer for supporting real time dataflow programs) and SMART [Kir89] that is concerned with real time performance for caches) The problem with each of these approaches is that issues that are not directly related to RTDB environments have to be resolved first. For example, the question of cache coherency has to be addressed in SMART to provide the real time ....

D. B. Kirk. SMART (Strategic memory allocation for real-time) cache design. In Proceedings of the Tenth Real-Time Systems Symposium, Santa Monica, California, pages 229--237, December 1989.

....system) cache invalidations and thus unexpected cache misses may occur when the execution of a task is resumed later on. Hardware and software approaches have been proposed to counter this problem but find little use in practice due to a loss of cache performance when caches are partitioned [20, 52, 29, 24]. Recently, attempts have been made to incorporate caching into rate monotone analysis and responsetime analysis [6, 7, 21] which allows WCET predictions for non preemptive systems to be used in the analysis of preemptively scheduled systems. This seems most promising since the information ....

D. B. Kirk. SMART (strategic memory allocation for real-time) cache design. In IEEE Real-Time Systems Symposium, pages 229--237, December 1989.

....and some temporal locality for simple loops. No general method to analyze the call graph of a task and control flow for each function was given. A few attempts have been made to improve the predictability of caches by architectural modifications to meet the needs of real time systems. Kirk [35] outlined such a system that relied on the ability to segment the cache memory into a number of dedicated partitions, each of which can only be accessed by a dedicated task. But this approach introduced new problems such as exhibiting lower hit ratios due to the partitioning and increasing the ....

....and predictability of accessing memory for real time systems by architectural modifications. One attempt by Kirk via cache partitioning has already been discussed in the last chapter, including some of the problems, such as lower hit ratios and increased complexity of scheduling analysis [35]. Cogswell and Segall suggest a different approach for the MACS architecture [17] which uses no cache memory. Instead, their pipelined processor performs a context swap between threads in a round robin ordering on each instruction. No thread may have more than one instruction in the pipeline at ....

D. B. Kirk. SMART (strategic memory allocation for real-time) cache design. In IEEE Symposium on Real-Time Systems, pages 229--237, December 1989.

....and some temporal locality for simple loops. No general method to analyze the call graph of a task and control flow for each function was given. A few attempts have been made to improve on the predictability of caches by architectural modifications to meet the needs of real time systems. Kirk [10] outlined such a system which relied on the ability to segment the cache memory into a number of dedicated partitions, each of which can only be accessed by a dedicated task. But this approach introduced new problems such as exhibiting lower hit ratios due to the partitioning and increasing the ....

D. B. Kirk. SMART (strategic memory allocation for real-time) cache design. In IEEE Symposium on Real-Time Systems, pages 229--237, December 1989.

....This type of cache misses cannot be avoided in real time systems with preemptive scheduling of tasks and results in a wide variation in task execution times. This execution time variation can be eliminated by partitioning the cache and dedicating one or more partitions to each real time task [14, 15]. This cache partitioning approach eliminates the cache unpredictability caused by task preemption. However, it still suffers from the cache unpredictability caused by intratask interference that will be explained next. Intra task interference in caches occurs when more than one memory block of ....

D. B. Kirk. SMART (Strategic Memory Allocation for Real-Time) Cache Design. In Proceedings of the 10th Real-Time Systems Symposium, pages 229--237, 1989.

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D. B. Kirk. SMART (strategic memory allocation for realtime) cache design. In Proceedings of 10th Real-Time Systems Symposium (RTSS'89), Dec. 1989.

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D. B. Kirk and J. K. Strosnider. Smart (strategic memory allocation for real-time) cache design using the mips r3000. pages 322--330, Lake Buena Vista, Florida, USA, Dec. 1990.

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D. B. Kirk. Smart (strategic memory allocation for real-time) cache design. In Proceedings of the 10th IEEE Real-Time Systems Symposium (RTSS89), pages 229--237, Santa Monica, California, USA, December 1989.

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D.B. Kirk. SMART (strategic memory allocation for real-time) cache design. In IEEE Real-Time Systems Symposium (RTSS), 1990.

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D. B. Kirk. SMART (strategic memory allocation for real-time) cache design. In IEEE Real-Time Systems Symposium, pages 229-237, December 1989.

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D. B. Kirk. SMART (Strategic Memory Allocation for Real-Time Cache Design. Proceedings of the 10th IEEE Systems Symposium, pages, 1989, 229-237.

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D. B. Kirk and J. K. Strosnider. Smart (strategic memory allocation for real-time) cache design using the mips r3000. In Proc. 11th Real-Time Systems Symposium, pages 322-- 330, Lake Buena Vista, Florida, USA, Dec. 1990.

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D. B. Kirk. Smart (strategic memory allocation for realtime) cache design. In Proc. 10th Real-Time Systems Symposium, pages 229--237, Santa Monica, CA, USA, Dec. 1989.

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D. Kirk. SMART #Strategic Memory Allocation for Real-Time# Cache Design. In IEEE Symposium on Real-Time Systems, pp 229#237, December 1989.

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