R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In IEEE RealTime Systems Symposium, pages 172--181, Dec. 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....power than accesses to larger or o# chip memories. Frameworks of WCET prediction are used to ensure that deadlines of tasks can be met. While the computation of WCET in presence of instruction caches has progressed in such a way that makes it possible to obtain an accurate estimate of the WCET [1, 2, 14], there has not been much progress with the presence of data caches. The main problem when dealing with data caches is that each load store instruction may access multiple memory locations (such as those that implement array or pointer accesses) Cache locking allows some or all of the contents ....

....the research in the area of predicting WCET of programs in presence of caches. Calculation of a tight WCET bound of a program involves di#culties that come from the very characteristics of data caching. Even though some progress has been done when studying processors with instruction caches [2, 14, 21], few steps have been done towards analyzing data caches. Alt et al. [1, 10] provide an estimation of WCET by means of abstract interpretation. As well as the usual drawbacks from abstract analysis (i.e. time consuming and lack of accuracy) they only analyze memory references which are scalar ....

R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In 15th Real-Time Systems Symposium, pages 172--181, 1994.

....than accesses to larger or o# chip memories. Frameworks of WCET prediction are used to ensure that deadlines of tasks can be met. While the computation of WCET in the presence of instruction caches has progressed in such a way that makes it possible to obtain an accurate estimate of the WCET [1, 2, 13], there has not been much progress with the presence of data caches. The main problem when dealing with data caches is that each load store instruction may access multiple memory locations (such as those that implement array or pointer accesses) Cache locking allows some or all of the contents ....

....the research in the area of predicting WCET of programs in presence of caches. Calculation of a tight WCET bound of a program involves di#culties that come from the very characteristics of data caching. Even though some progress has been done when studying processors with instruction caches [2, 13, 20], few steps have been done towards analyzing data caches. Alt et al. [1, 9] provide an estimation of WCET by means of abstract interpretation. As well as the usual drawbacks from abstract analysis (i.e. time consuming and lack of accuracy) they only analyze memory references which are scalar ....

R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In Proceedings of 15th Real-Time Systems Symposium (RTSS'94), pages 172--181, 1994.

....of the WCMP, and thus for the WCET as well. Frameworks of WCET prediction are used to ensure that deadlines of tasks can be met. While the computation of WCET in the presence of instruction caches has progressed in such a way that makes it possible to obtain an accurate estimate of the WCET [1, 2, 8], there has not been much # email: xavier.vera mdh.se 1 progress with the presence of data caches. The main problem when dealing with data caches is that each load store instruction may access multiple memory locations (such as those that implement array or pointer accesses) 1.1 Coyote ....

R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding worstcase instruction cache performance. In Proceedings of 15th Real-Time Systems Symposium (RTSS'94), pages 172--181, 1994. 7

....Table 1: Overall timing intervals [c i;min ; c i;max ] for StrongARM simulation of PrS of different benchmarks from [16] cache simulation are compared in table 1. The circle benchmark is a circle drawing routine from Gupta [9] the bubble sort is an example by Ye with 15 elements taken from [2]. Check data from Park [20] checks if an array element is negative while the key is a part of a chroma key video application from [11] The name of the benchmark is shown in the first column followed by the total number of PrS nodes in the syntax graph and their classification to SFP, CDP or ....

R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding worst case instruction cache performance. In Proceedings of the IEEE RealTime Systems Symposium, pages 172--181, December 1994.

....published on WCET analysis for modern processors is focused on just one architectural feature: program path analysis, instruction caching, data caching, or pipelining. Combined analysis approaches tend to have either a high computational complexity or a weakness in some parts of the analysis. In [Arn94] a technique is described to statically predict which instructions will be in the instruction cache during program execution. In this approach, called Static Cache Simulation, instructions are classified as always hit, always miss, first miss and first hit, by analyzing the control flow of the ....

Arnold, R., F. Mueller, D. Whalley, and M. Harmon, Bounding Worst-Case Instruction Cache Performance, in Proceedings of the 15th Real-Time Systems Symposium, pp. 172-181, 1994.

....a correct function. Adding caches to a real time system is a non trivial task since the execution time will become variable depending if the executing instruction or accessed data is in the cache or not. Some methods have nevertheless successfully been able to make system with caches analyzable [2, 3, 4, 5, 6, 7], but they all aim at WCET analysis. To the best of our knowledge no one has tried to bound WCCMR, even if many of the WCET analysis algorithms with some modifications would be able to perform such analysis. The major difference between the adjacent work and our proposition is the simplicity of ....

....manageable and reduce the analysis time will be developed. It might however not be possible without approximations with a looser bound of WCCMR as a result. The method will also be developed to handle temporal locality. This can be achieved by including a static cache simulator as for instance in [3]. With this extension a tighter bound of c2 c7 c3 c8x c8n c4x c4n c9x c9n c9x c9n c5 c5 c11 c11 c11 c11 c11 c11 (a) b) c) d) e) f) Figure 4: The binary search tree to find the WCCMR. The node labels corresponds to the node labels in Figure 3. The suffix n and x in some nodes ....

Robert D. Arnold, Frank Mueller, David B. Whalley, and Marion G. Harmon. Bounding worst-case instruction cache performance. In Proceedings of the IEEE RealTime Systems Symposium 1994.

....for nested loops that reflects the position of a loop relatively to its enclosing and enclosed loops (see figure 2) Each loop is associated with a loop nesting level (In level for short) In the following, a loop whose ln level is a will be referred as loop a. Top level loops are named [0] [1], etc. Loops enclosed by loop [0] are named [0.0] 0.1] and so on. We also define ln level [ which is the level enclosing the whole syntax tree. For example, a loop whose ln level is [2.3.1.0] is enclosed in loops [2.3.1] 2.3] 2] and lastly [ We add a dummy ln level named never, upper ....

....in a cache miss (it is the most pessimistic case) first miss: the first reference of the iblock results in cache miss and cache hit for subsequent iblock references. conflict: the iblock reference results in either hit or miss depending on the flow of control. F. Mueller pointed out in [1] that since the program may consist in a number of nested loops, an instruction must be assigned a category for each loop nesting level. Our approach is slightly different. We associate a ln level with each iblock. This associated ln level points out the loop where conflicting access to ....

R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding worst-case instruc- tion cache performance. In Proc. of IEEE Symposium on Real-Time, pages 172-181, December 1994.

....the tight bound on worst case performance of the systems. Especially, worst case performance analysis is extremely important for ecient implementation of hard real time systems in which real time constraints have to be satis ed. There are a number of previous researchefforts, for example [1, 3, 9, 10], to estimate the tight bound on worst case execution time of a given task in a single task environment. However, they cannot directly be applied for preemptivemultitask systems because they do not takeinto account intertask cache interference, called Cache Related Preemption Delay (CRPD) CRPD is ....

R. D. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon, \Bounding worst-case instruction cache performance," In ##### ## ######### ####### #####, pp. 172-181, 1994.

.... to be able to do so for high level languages [37, 30] Since Shaw proposed timing schema for analyzing system running time based on high level languages [37] a number of people have extended it for analysis in the presence of compiler optimizations [30, 10] pipelining [17, 24] cache memory [3, 24, 12], etc. However, there is still a serious limitation of the timing schema, even in the absence of lowlevel complications. This is the inability to provide loop bounds, recursion depths, or execution paths automatically and accurately for the analysis [29, 2] For example, the inaccurate loop bounds ....

....of primitive parameters for various compilers, run time systems, operating systems, and machine hardwares. In recent years, much progress has been made in analyzing low level dynamic factors, such as clock interrupt, memory refresh, cache usage, instruction scheduling, and parallel architectures [30, 3, 24, 12]. Nevertheless, the inability to compute loop bounds or execution paths automatically and accurately has led calculated bounds to be much higher than measured worst case time. In programming language area, Rosendahl proposed using partially known input structures [32] For example, instead of ....

R. Arnold, F. Mueller, D. B. Whalley, and M. G. Harmon. Bounding worst-case instruction cache performance. In Proceedings of the 13th IEEE Real-Time Systems Symposium. IEEE CS Press, Los Alamitos, Calif., 1994.

....challenges to conventional re engineering methodologies which are not mature yet as design methodologies. Thus, they propose to use re engineering patterns drawn from their experience [16] For hardware re engineering, most research focuses on cost effective hardware upgrades. Madisetti et al. in [1 1] propose a systematic technique for rapidly upgrading electronic systems. They propose to use virtual prototyping accompanied by their tools and libraries of simulatable models. Their approach is to evaluate the cost and benefit of re engineering while performing hardware software cosimulation. To ....

....To facilitate electronic hardware re engineering, Tummala and Madisetti in [18] show that the SoP (System on a Package) paradigm provides more architectural flexibility, thus enabling the re engineering at a lower cost than the SoC (System on a Chip) paradigm. The re engineering approaches in [1 1, 18] are similar to ours in a sense that they adopt hardware upgrades as a way of re engineering. This paper is organized as follows. Section 2 defines the application model of an embedded real time system along with its timing and performance constraints. Section 3 presents as our first step the ....

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R. Arnold, F. Mueller, and D. Whalley. Bounding worstcase instruction cache performance. In Proceedings oflEEE Real-Time Systems Symposium, pages 172 181, December 1994.

....prediction is one of our main future research topics. All memory accesses are cache hits. This assumption is to ignore the effect of cache misses on the execution time. Since our approach does not make any assumption on the cache system, previously proposed techniques on the cache analysis [1, 11, 10] can easily be integrated with our approach. Processor can issue up to k instructions simultaneously, where k is provided as a parameter to our analysis. k is equal to or smaller than the number of functional units in the processor (i.e. k 9 in our processor model) We further assume that ....

....the merging operation. The IDG shown in Figure 7(b) includes the distance bounds between nodes as well as the weights between nodes. In Figure 7(b) the nodes that can be merged are shown inside a dotted box. For example, nodes 2 and 3 can be merged because the distance bounds between them are [1, 1]. Nodes 5, 6 and 7 can be merged as well because they have the distance bounds [0, 0] and [4, 4] Since merged nodes (except for the first node) have a constant distance on their issue times relative to the first node, no information is lost in predicting the WCETs by the merging operation. On the ....

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R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding Worst-Case Instruction Cache Performance. In Proceedings of the 15th Real-Time Systems Symposium, pages 172 181, 1994.

....a timing analyzer based on a mathematical model of the pipelined Intel 80C188 processor. This analysis method is able to take into account the overlap between instruction execution and fetching, which is an improvement over schemes where instruction executions are treated individually. In [31] Arnold et al. developed a timing prediction method called static cache simulatiotz to statically analyze memory and cache reference patterns. A similar but more advanced approach was reported in [23] While the latter approach is able to predict pipeline stalls as well, both essentially rely on ....

....essentially rely on attribute grammars [2] to propagate cache hit information backward in a flow graph. However, no static timing tool is precise enough to be used with complete confidence for de veloping production quality software. Moreover, even sophisticated timing analysis methods such as [23, 31] are not appropriate for fine grained instruction timing. In Section 3.3 we explain how we can effectively use these tools in spite of the limitations, by also taking advantage of software profiling, as well as static timing prediction. Specifically, our slicing technique does not require any ....

D. Whalley R. Arnold, F. Mueller. Bounding worst-case instruction cache performance. In Press, December 1994.

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R. Arnold, F. Mueller, D. Whalley, and M. Harmon, "Bounding Worst-Case Instruction Cache Performance," Proceedings of the Fifteenth IEEE Real-Time Systems Symposium, pp. 172-181 (December 1994).

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R. Arnold, F. Mueller, D. B. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In IEEE Real-Time Systems Symposium, pages 172--181, Dec. 1994.

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R. Arnold, F. Mueller, D. B. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. IEEE RealTime Systems Symposium, pp. 172-181, Dec. 1994.

....designer to budget enough processing power to handle worst case computational requirements and safely meet deadlines under any circumstance. Sophisticated timing analyzers can calculate safe, tight WCET bounds for tasks executing on single issue inorder pipelines with instruction and data caches [2,11,12,14,15,16,17,18,26,34,42]. However, the level of sophistication needed to safely and accurately analyze more complex architectures is formidable. Currently, there is no way to precisely specify microarchitectures with a full complement of high performance techniques (complex dynamic branch predictors, caches, deep ....

....loop bodies only require a few traversals to bound the WCET for the entire loop. We capture the worst case behavior of architectural components along execution paths and compose these paths for loops, functions, and, ultimately, the entire application, to derive cycle counts that bound the WCET [1,2,11,23,24,25,26,27,38,39,40]. Figure 1 shows the organization of the timing analysis environment, which has been adapted to model the VISA and the Simplescalar instruction set (PISA) 6] The application is compiled to assembly code using the gcc PISA compiler. Control flow and instruction data memory references are ....

[Article contains additional citation context not shown here]

R. Arnold, F. Mueller, D. B. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. Real-Time Systems Symp., Dec. 1994.

....real time systems relies on #######knowledge of the worst case execution time (WCET) of hard real time tasks to check if the deadline of a task can be met. A safe upper bound on the WCET of a task can be provided through static analysis, dynamic analysis or even a combination of both techniques [34, 30, 15, 41, 24, 16, 1, 22, 23, 9, 29, 38]. Regardless of the methods utilized to obtain the WCET of tasks, experiments show a wide variation between longest and shortest execution times for manyembedded applications. In [38] execution times of real world embedded tasks vary by as much as 87 relative to their measured WCET. Speci ....

R. Arnold, F. Mueller, D. B. Whalley,and M. Harmon. Bounding worst-case instruction cache performance. In #### ######### ####### #########, pages 172-181, December 1994.

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R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In IEEE RealTime Systems Symposium, pages 172--181, Dec. 1994.

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R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In IEEE RealTime Systems Symposium, pages 172--181, Dec. 1994.

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R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In IEEE RealTime Systems Symposium, pages 172--181, Dec. 1994.

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R. Arnold, F. Muller, D. Whalley, and M. Harmon. Bounding Worst-Case Instruction Cache Performance. In Proc. 15 (RTSS'94), pages 172--181, 1994.

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R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding Worst-Case Instruction Cache Performance. In Proceedings of the 15th Real-Time Systems Symposium, pages 172-- 181, 1994.

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R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding worst-case instruction cache performance. In Proceedings of 15th Real-Time Systems Symposium (RTSS'94), pages 172--181, 1994.

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R. Arnold, F. Mueller, and D. Whalley. Bounding Worst-Case Instruction Cache Performance. In Proceedings of the 15th IEEE Real-Time Systems Symposium (RTSS), Dec. 1994.

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R. Arnold, F. Mueller, D. Whalley, and M. Harmon. Bounding WorstCase Instruction Cache Performance. In Proceedings of the fifteenth IEEE Real-Time Systems Symposium, pages 172--181, Brookline, Massachusetts, December 1994. IEEE press.

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