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R.K. Brayton, et al. Logic Minimization Algorithms for VLSI Synthesis, Boston, MA, Kluwer Academic Publishers, 1984

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Simplification of Non-Deterministic Multi-Valued Networks - Mishchenko, Brayton (2002)   Self-citation (Brayton)   (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, A. L. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Dordrecht, 1984.


Higher-Order Flexibilities in Multi-Valued Networks - Mishchenko, Brayton (2002)   Self-citation (Brayton)   (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, A. L. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Dordrecht, 1984.


A Theory of Non-Deterministic Networks - Alan Mishchenko And (2003)   Self-citation (Brayton)   (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Dordrecht, 1984.


A Theory of Non-Deterministic Networks - Alan Mishchenko And (2005)   Self-citation (Brayton)   (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, A. L. SangiovanniVincentelli, Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Dordrecht, 1984.


A Boolean Paradigm in Multi-Valued Logic Synthesis - Alan Mishchenko Robert (2002)   Self-citation (Brayton)   (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, A. L. SangiovanniVincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Dordrecht, 1984.


Postgraduate Study Report DC-PSR-2004-14 - Mixed-Mode Bist Based   (Correct)

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R.K. Brayton, et al. Logic Minimization Algorithms for VLSI Synthesis, Boston, MA, Kluwer Academic Publishers, 1984


Column-Matching BIST Exploiting Test Don't-Cares - Petr Fiser Jan (2003)   (Correct)

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Brayton, R.K, et al.: Logic Minimization Algorithms for VLSI Synthesis, Boston, MA, Kluwer Academic Publishers, 1984


Minimization and Partitioning Method Reducing Input Sets - Jan Hlavicka Petr   (Correct)

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R.K. Brayton et al., Logic minimization algorithms for VLSI synthesis. Boston, MA, Kluwer Academic Publishers, 1984


Mixed-Mode Bist Based On Column Matching - Petr Fiser Informatics (2004)   (Correct)

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Brayton, R.K, et al.: Logic Minimization Algorithms for VLSI Synthesis, Boston, MA, Kluwer Academic Pub., 1984


FC-Min: A Fast Multi-Output Boolean Minimizer - Petr Fiser Jan (2003)   (Correct)

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R.K. Brayton et al., "Logic minimization algorithms for VLSI synthesis", Boston, MA, Kluwer Academic Publishers, 1984, 192 pp.


Computing and Informatics, Vol. 22, 2003, 1001--1033, V.. - Boom Heuristic Boolean   (Correct)

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Brayton, R. K. et al.: Logic Minimization Algorithms for VLSI Synthesis. Boston, MA, Kluwer Academic Publishers, 1984.


The Iterative Boolean Minimizer Fc-Min - Petr Fiser Supervisor   (Correct)

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R.K. Brayton et al., "Logic minimization algorithms for VLSI synthesis", Boston, MA, Kluwer Academic Publishers, 1984, 192 pp.


partial10 4/2/2000 11:55 PM - Algorithm For Minimization   (Correct)

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BRAYTON, R.K. et al.: Logic minimization algorithms for VLSI synthesis. Boston, MA, Kluwer Academic Publishers, 1984


Single-Level Partitioning Support In Boom-Ii - Petr Fiser Hana (2004)   (Correct)

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Brayton, R.K., et al. (1984). Logic minimization algorithms for VLSI synthesis, 192 pp., Boston, MA, Kluwer Academic Publishers.


Two-Level Boolean Minimizer BOOM-II - Petr Fiser Hana (2004)   (Correct)

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R.K. Brayton et al.: Logic minimization algorithms for VLSI synthesis, Boston, MA, Kluwer Academic Publishers, 1984, 192 pp.


Boolean Minimizer FC-Min: Coverage Finding Process - Petr Fiser Hana   (Correct)

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R.K. Brayton et al., "Logic minimization algorithms for VLSI synthesis", Boston, MA, Kluwer Academic Publishers, 1984, 192 pp.


Efficient Minimization Method For - Incompletely Defined Boolean   (Correct)

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BRAYTON, R.K. et al.: Logic minimization algorithms for VLSI synthesis. Boston, MA, Kluwer Academic Publishers, 1984


Behavioral Level Guidance Using Property-Based Design.. - Lisa Marie Guerra (1996)   (1 citation)  (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Boston, MA, 1984.


Low Power Architectural Design Methodologies - Landman (1994)   (22 citations)  (Correct)

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R. Brayton, G. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, 1984.


A Fast Algorithm for OR-AND-OR Synthesis - Debnath, Vranesic (2003)   (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. Norwell, MA: Kluwer, 1984.


Reusing Code in Genetic Programming - Edgar Galvan Lopez (2004)   (Correct)

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R. K. Brayton, G. D. Hachtel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984. 10


State Assignment based on Two-dimensional Placement and - Hypercube Mapping   (Correct)

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R. K. Brayton, G. D. Hatchtel, C. T. McMullen and A. L. Sangiovanni Vincentelli, "Logic Minimization Algorithms for VLSI Synthesis," Kluwer Academic, 1984.


Unknown -   (Correct)

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Brayton, R. K., Hachtel, G. D., McMullen, C. T., and Sangiovanni-Vincentelli, A. L.: `Logic Minimization Algorithm for VLSI Synthesis', Kluwer Academic Publishers, Boston, 1984


Power Minimization in IC Design: Principles and Applications - Pedram (1996)   (72 citations)  (Correct)

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R. K. Brayton, G. D. Hachtel, C. McMullen and A. L. Sangiovanni-Vincentelli. " Logic minimization algorithms for VLSI synthesis. " Kluwer Academic Publishers, Boston, Massachusetts, 1984.


LowPower State AssignmentTargeting Twoand - Multi-Level Logic Implementations   (Correct)

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R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Boston, Massachusetts, 1984.

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