S. Ramanathan and V. Visvanathan, "Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay," INTEGRATION, the VLSI journal, vol. 27, no. 1, pp. 1-32, Jan. 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....implements a given filtering operation. There is no significant degradation in performance when multirate FIR algorithms are mapped on the CE in comparison to their respective base architectures. We intend to explore other most often used DSP algorithms (including adaptive filtering algorithms [30]) to come up with a single computational engine with superior performance suitable for emerging compute intensive powercritical DSP applications. ....

S. Ramanathan and V. Visvanathan, "Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay," INTEGRATION, the VLSI journal, vol. 27, no. 1, pp. 1-32, Jan. 1999.

....10 2 10 1 10 0 10 1 Iteration 64 32 16 8 0 MSE Fig. 3. Convergence plots for subband DNLMS algorithm In this paper, we first synthesize a pipelined subband DNLMS adaptive filter architecture with minimal adaptation delay for any given sampling rate, based on the technique described in [25] [28] and the synthesis methodology for decimation interpolation filter architectures described in the following section. The transformation based synthesis methodology uses a sequence of function preserving transformations on the SFG representation of the algorithm to arrive at the final ....

....is correct by construction. The standard transformations used are holdup, associativity of addition, retiming [29] slowdown and folding [30] The use of such transformations for optimizing area speed power is well known [31] 32] However, its use in improving algorithmic robustness is novel [25] [28] Apart from these standard transformations, the methodology also uses some special function preserving transformations which were introduced in [25] 28] Using carry save arithmetic, the fine grain pipelined architecture has a critical path consisting of two full adders and a 2 to 1 ....

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S. Ramanathan and V. Visvanathan, "Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay," INTEGRATION, the VLSI journal, vol. 27, no. 1, pp. 1-32, Jan. 1999.

....The resulting folded architecture is shown in Fig. 11. The control circuit consists of 2to 1 and P to 1 P periodic multiplexers and folded arcs with synchronization registers [2] The negative delays present in the input path of the folded architecture can be neutralized by retiming [24] [25] appropriate delays from the corresponding output accumulation path. Further, using m ( l Tm TP Gammato Gamma1 Ta T 2 Gammato Gamma1 m , where T P Gammato Gamma1 and T 2 Gammato Gamma1 are the delays associated with P to 1 and 2 to 1 P periodic multiplexers and Tm and T a are the delays ....

.... and the P to 1 P periodic multiplexer present in the feedforward paths of the folded architecture are pipelined to obtain a critical path delay (T crit ) of (T a T 2 Gammato Gamma1 ) Note that, the above mentioned retiming and pipelining transformations uses the generalized retiming theorem [25]. With the further use of this theorem and additional holdup registers, register minimization can be achieved. The final pipelined architecture shown in Fig. 12 consists of a boundary processor module (BPM) and F identical folded processor modules (FPMs) The multiplexer definitions based on the ....

[Article contains additional citation context not shown here]

S. Ramanathan and V. Visvanathan, "Low-power pipelined LMS adaptive filter architecture with minimal adaptation delay," INTEGRATION, the VLSI journal, vol. 27, no. 1, pp. 1-32, Jan. 1999.

..... The resulting folded architecture is shown in Fig. 11. The control circuitry consists of 2 to 1 and P to 1 P periodic multiplexers and folded arcs with synchronization registers [2] The negative delays present in the input path of the folded architecture can be neutralized by retiming [23] [24] appropriate delays from the corresponding output accumulation path. Further, using m ( l Tm TP Gammato Gamma1 Ta T2 Gammato Gamma1 m , where TP Gammato Gamma1 and T 2 Gammato Gamma1 are the delays associated with P to 1 and 2 m m H (P D m 2) a a a P 1 a N P a N P 1 a N 1 . ....

.... and the P to 1 P periodic multiplexer present in the feedforward paths of the folded architecture are pipelined to obtain a critical path delay (T crit ) of (T a T 2 Gammato Gamma1 ) Note that, the above mentioned retiming and pipelining transformations uses the generalized retiming theorem [24]. With the further use of this theorem and additional holdup registers, register minimization can be achieved. The final pipelined architecture shown in Fig. 12 consists of a boundary processor module (BPM) and F identical folded processor modules (FPMs) The multiplexer definitions based on the ....

S. Ramanathan and V. Visvanathan, "Low-power pipelined LMS adaptive filter architecture with minimal adaptation delay," to appear in INTEGRATION, the VLSI journal.

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