J. Costa, J. Monteiro, and S. Devadas. Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 184--189, August 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....circuits still meet timing constraints. Key words: domino logic circuits, phase assignment, low power synthesis I Introduction The advent of portable digital devices such as laptop computers and cellular phones has made low power circuit design an increasingly important research area [4, 13, 14, 12, 6, 11]. For example, laptop computers have a limited battery life, and so the circuitry in the computer must be designed to dissipate as little power as possible without sacrificing performance in terms of speed. Further more, simultaneous low power and high performance designs are needed beyond the ....

J. C. Costa, J. C. Monteiro, and S. Devadas, "Switching activity estimation using limited depth recon- vergent path analysis," Int. Symposium on Low Power Electronics and Design, pp. 184-189, 1997.

.... have been developed to solve certain issues at all design levels [1] Also, a number of power estimation methods for combinational logic circuits have been developed [2] Recently, a number of probabilistic estimation methods, considering zero gate delay model [3,4,5] and real gate delay model [6,7], were proposed. The method presented in [5] is the most accurate assuming zero delay gate model since all types of correlations among the circuit signals are considered. The temporal correlation was captured by modelling the behaviour of a signal as a two state Markovian stochastic process, while ....

....as a two state Markovian stochastic process, while the spatial correlation by the introduction of the concepts of the spatiotemporal transition correlation coefficient and the signal isotropy. Assuming arbitrary gate delay model, a few probabilistic power estimation methods have been published [6,7]. In [6] a symbolic simulation algorithm has been proposed. Given the switching activities of the primary inputs and using OBDDs, the transition probability of a node at time t resulted by XORing the Boolean functions that correspond to two successive switching time instances, i.e. t and t 1. The ....

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J.C. Costa, J.C. Monteiro, and S. Devadas, "Switching Activity Estimation using Limited Depth Reconvergent Path analysis", In Proc. of ISLPD, pp. 184-189, 1997.

....parameter in the modem VLSI design field[1] The average number of transitions of the circuit nodes can express the average power consumption of a circuit. A variety of probabilistic power estimation methods have been developed to estimate the power consumption of the combinational circuits [2] [9]. In this methods probabilistic properties, such as the average steady state and the average transition probability of the circuit nodes, are used in order to evaluate the transitions of any circuit node. The above methods can be classified according to assumed gate delay model in the following ....

....are used in order to evaluate the transitions of any circuit node. The above methods can be classified according to assumed gate delay model in the following categories i) the zero delay methods [3] 6] where only the functional transitions are considered and the ii) real gate delay methods [7] [9], where both the functional and spurious transitions are taken into account. Hence, real gate delay model is needed for accurate power estimation. In addition temporal correlation, input pattem dependencies and spatial (structural) dependencies have to be considered to estimate accurate the power ....

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J.C. Costa, J.C. Monteiro, and S. Devadas, "Switching Activity Estimation using Limited Depth Reconvergent Path analysis", In Proc. of ISLPD, pp. 184-189, 1997.

....power, sometimes even more) In [GDKW92] Ghosh et al. proposed an exact method to estimate the switching activityundergeneral delay, but this is based on global BDDs, which may be very time consuming for large circuits. Recently, the Polynomial Simulation, referred here as PS, was proposed in [CMD97]. The PS method allows a good performance accuracy tradeoff for activity computation under general delay, controlled by a single parameter l. This parameter controls the depth to which reconvergence of signals is taken into account: this method is called limited depth approach. The switching ....

....1: f = p b (1) To reduce the complexity of the polynomials some variables may be substituted by their probability values. The reason why the substitution can be applied is because the variables outside the reconvergent path will not generate spatial correlation. In the PS approach [CMD97], the polynomials were implemented by a list of sets. Each set is implement by a binary vector, a coefficient, and an ordered list of active variables. For example, p = 0:5 Theta a 0:3 Theta a ) is implemented by a list = 0:5 Thetaf0100 z 0001 z b g# 0:3 ....

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Jose C. Costa, Jose C. Monteiro, and Srinivas Devadas. Switching activity estimation using limited depth reconvergent path analysis. In Proceedings of the 1997 international symposium on Low power electronics and design, pages 184--189, 1997.

....without the need for an exponentially long description of the input stimuli. These methods usually assume simplified models of temporal and spatial correlations. One common simplification is the assumption that the primary inputs are uncorrelated in time and space. Both exact [5] and approximate [2] algorithms, for this problem have been proposed. Methods that use a more accurate modeling of spatial and temporal correlations have also been presented. One such method [9] models the pairwise spatial correlations of the primary inputs and propagates them through the circuit. A different ....

J. Costa, J. Monteiro, and S. Devadas. Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 184--189, August 1997.

....proposed an exact method to estimate the switching activity under general delay, but this is based on global BDDs, which may be very time consuming for large circuits. Various heuristic approaches were thus developed [10] Recently, the Polynomial Simulation, referred here as PS, was proposed in [2]. The PS method derives from an exact method [9] and is parameterized by a single parameter l, determining the speed accuracy tradeoff. This allows the user to improve the accuracy at the expense of runtime. We developed a new efficient implementation of the polynomial simulation method (PS) ....

....method derives from an exact method [9] and is parameterized by a single parameter l, determining the speed accuracy tradeoff. This allows the user to improve the accuracy at the expense of runtime. We developed a new efficient implementation of the polynomial simulation method (PS) proposed in [2], to compute the switching activities in a combinational logic circuit using a general delay model. This implementation improves the local power computation, with a particular treatment of the active variables and a new polynomial representation. We will first review the classical PS method, then ....

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Costa, J. C., Monteiro, J. C., and Devadas, S. Switching activity estimation using limited depth reconvergent path analysis. In Proceedings of the 1997.

....by CSI INPG. III. POWER ESTIMATES In these last years, the DICE Laboratory at UCL has developped an efficient and flexible power estimation tool to compute the switching activity of CMOS digital designs [3] which is a sensible improvement of the former Polynomial Simulation presented by Costa [4]. Fig. 1. Speedup of gate level power estimator on large benchmarks. This new power estimator may handle large combinational circuits. It takes into account simultaneous multiple input transitions, temporal and structural correlation of the circuit and assumes that primary inputs are ....

....circuits, thanks to three main improvements: 1. an efficient local node computation, 2. a simplified inverter handling to lower the effective gate depth, 3. an improved polynomial representation for computing the signal transition probability. Compared to the PS results reported in [4] on a set of benchmark circuits, our results show the efficiency of the proposed method (Fig. 1. It should be noted that the exact method, which is more rapid than the PS one in most examples, does not succed to compute the C880 example. This tool was extended at higher levels, to derive an ....

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J. Costa, J. Monteiro, S. Devadas, "Switching activity estimation using limited depth reconvergent path analysis.", Proceedings of International Symposium on Low Power Electronics and Design, pp.184-189, 1997.

....ones. Moreover, considering the assumed gate delay model they are also characterized as zero and real gate delay methods. A survey of the power estimation methods for combinational logic circuits has been reported in [2, 3] Assuming zero gate delay model [4, 5] and real gate delay model [6,7,8,9], a number of probabilistic power estimation methods have been presented. In particular, a method for calculating the switching activity of the circuit nodes, using Order Binary Decision Diagrams (OBBDs) was proposed [4] Modeling the behavior of the logic signal as an one step Markovian process ....

....simulation algorithm has been proposed using OBDDs. The structural and the first order temporal correlation were handled but the input pattern dependency was not considered. A new method for calculating the transition probabilities by performing symbolic polynomial simulation was proposed in [9]. It is based on the signal probability evaluation method of [11] which has been extended to handle temporal correlation and arbitrary transport gate delay models. The method was parameterized by a single factor, which determines the circuit levels over which the structural correlation is ....

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J.C. Costa, J.C. Monteiro, and S. Devadas, "Switching Activity Estimation using Limited Depth Reconvergent Path analysis", in Proc. of Int. Symp. On Low Power Electronics and Design (ISLPED), pp. 184-189, Monterey CA, August 18-20, 1997.

....model. For both problems our algorithms attain good power savings when the resulting circuits are measured under a general delay model by the power estimation tool in Berkeley SIS. In Section 4. 2 we present our power estimation method which is a simplification of a more general scheme presented in [6]. In Section 4.3 we present the algorithm and experimental results for low power technology decomposition of simple gates. In Section 4.4 we present the algorithm and experimental results for the low power retiming of sequential circuits. Finally, in Section 4.5 we summarize our work and present ....

....Second, the algorithm can easily be modified to estimate transitions under a general delay model by using accurate delay information to determine the exact transition times of fanins to a gate. We note that this algorithm turns outs 57 to be a simplification of a more general approach proposed in [6]. In that work, the authors modify the Parker McCluskey method [32] to compute switching activities under a general delay model. Their algorithm takes as a parameter the number of levels in the transitive fanin of each gate that should be considered to account for spatial correlations due to ....

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J. Costa, J. Monteiro, and S. Devadas. Switching activity estimation using limited depth reconvergent path analysis. In International Symposium on low power electronics and design, pages 184--189, 1997.

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J. Costa, J. Monteiro, and S. Devadas. Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 184--189, August 1997.

No context found.

J. Costa, J. Monteiro, and S. Devadas. Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 184--189, August 1997.

....be time consuming. However, the evaluation step, which is repeatedly called during the RTL synthesis to compute the power of the functional unit, should be simple and fast. In this work, we propose a bottom up approach based on ZBDDs that uses the gate level polynomial simulation (PS) method [7, 8] to estimate the power of RTL circuits. Our approach extracts parameters from the lower design abstraction level to build an efficient and accurate model at high level. Our approach is probabilistic, and therefore does not suffer from input pattern dependence. It also offers a tradeoff ....

....are not taken into account. More recently, Costa et al. 6] proposed a probabilistic approach which takes into account the glitch power. This approach can handle different input statistics and builds a bottom up model from the gate level analysis. The approach is based on polynomial simulation PS [7] to compute the power estimation at gate level. The PS method substitutes some variables by their probability values to reduce the size of the probability polynomials. However, this reduction can not be applied in RTL estimations, because we need to express the polynomial in terms of the primary ....

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J. C. Costa, J. C. Monteiro, and S. Devadas. Switching activity estimation using limited depth reconvergent path analysis. In Proceedings of the 1997.

....over 90 of the total power dissipation. Thus power optimization techniques at different levels of abstraction target minimal switching activity power. The model for power dissipation for a gate i in a logic circuit is simplified to: 2) Both simulation based (e.g. 4] and probabilistic (e.g. [8]) techniques have been proposed for the computation of . Simulation based techniques use a logic or timing simulator. The circuit is simulated with a sufficiently large number of randomly generated input vectors to obtain an average transition count at every gate in the circuit. Simulation based ....

J. C. Costa, J. C. Monteiro and S. Devadas, "Switching Activity Estimation using Limited Depth Reconvergent Path Analysis", in Proceedings of the International Symposium on Low Power Design, 1997.

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J. Costa, J. Monteiro, and S. Devadas. Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 184--189, August 1997. The related estimation problems ask for the actual value of the peak or average power.

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J. C. Costa, J. C. Monteiro, and S. Devadas. Switching Activity Estimation using Limited Depth Reconvergent Path Analysis. In Proceedings of the International Symposium on Low Power Design (ISLPD), 1997.

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J. C. Costa, J. C. Monteiro and S. Devadas, "Switching Activity Estimation using Limited Depth Reconvergent Path Analysis", in Proceedings of the International Symposium on Low Power Design, 1997.

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J. Costa, J. Monteiro, and S. Devadas, "Switching activity estimation using limited depth reconvergent path analysis," in Proceedings of the International Symposium on Low Power Electronics and Design, pp. 184 --189, 1997.

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J. C. Costa, J. Monteiro, and S. Devadas. Switching activity estimation using limited depth reconvergent path analysis. In International Symposium on low power electronics and design, pages 184 189, 1997.

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