Tse-Yu Yeh and Yale N. Patt. A comprehensive instruction fetch mechanismfor a processor supporting speculative execution. In 25th Annual International Symposium on Microarchitecture, pages 129--139, Portland, Or, December 1992. ACM.  Home/Search   Document Not in Database   Summary   Related Articles

....in x8. 2 Prior Branch and Fetch Prediction Research This section briefly surveys prior work on branch prediction techniques used in this paper. Branch target buffers (BTB) have been used as a mechanism for branch and instruction fetch prediction, effectively predicting the behavior of a branch [1, 7, 10, 13, 15, 21]. The Intel Pentium is an example of a modern architecture using BTBs it has a 256 entry BTB organized as a four way associative cache. Only branches that are taken are entered into the BTB. If a branch address appears in the BTB and the branch is predicted as taken, the stored address is ....

....record the percentage of misfetched branches ( MfB) and the percentage of mispredicted branches ( MpB) Note that a mispredicted branch is never counted as a misfetched branch and visa versa. It is often difficult to understand how each of these metrics influence processor performance. Yeh Patt [21] defined the branch execution penalty to be: BEP = MfB Theta misfetch penalty MpB Theta misprediction penalty 100 : The BEP reflects the average penalty suffered by a branch due to misfetch and mispredict penalties. With a BEP of 0:5, the average branch incurs a half cycle execution ....

Tse-Yu Yeh and Yale N. Patt. A comprehensive instruction fetch mechanismfor a processor supporting speculative execution. In 25th Annual International Symposium on Microarchitecture, pages 129--139, Portland, Or, December 1992. ACM.

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