R. Harjani, R. A. Rutenbar, and L. R. Carley, "Analog Circuit synthesis for Performance in OASYS," Proc. International Conference on Computer-Aided Design, November, 1988, pp. 492-495. [Some comparators in OASYS] 154 Home/Search Document Not in Database Summary Related Articles Check |
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MIDAS - a functional simulator for mixed digital and analog.. - Williams, Wooley (1995) (1 citation) (Correct)
....an optimization algorithm many times. In practice these approaches do reach solutions quickly, but they do can not guarantee any optimality for the result. Also, these design recipes are unique to each topology, and must be re implemented. as part of every new module [ALLE85, DEGR87, BERK88, HARJ88, MAKR92] Some selection techniques use a combination of heuristic topology selection with low level device optimization [FOTO94, KOH89, ONOD90] 1.2.3 Layout Automation Analog layout synthesis is the process by which a circuit description is used to create the actual mask geometries for the ....
....into subcell specifications, develop sub module generators and create the subcells to these specifications. Several analog synthesis approaches use a high degree of hierarchical decomposition, using simple circuit elements such as differential pairs and current sources and current mirrors [BERK88, HARJ88] In a design with significant interaction between the subcells, the decomposition step is difficult. In a knowledge based framework, the top down decomposition again follows a designer recipe, with the limitations to preprogrammed topologies. In an optimization based framework, the process of ....
R. Harjani, R. A. Rutenbar, and L. R. Carley, "Analog Circuit synthesis for Performance in OASYS," Proc. International Conference on Computer-Aided Design, November, 1988, pp. 492-495. [Some comparators in OASYS] 154
Optimum Stacked Layout for Analog CMOS ICs - Malavasi, Pandini, Liberali (1993) (Correct)
....the respect of high level specifications is guaranteed in all design stages. However, a severe discontinuity is present between schematic definition and physical implementation. Most of the existing tools for high level architectural selection and circuit sizing are based on numeric optimization [5, 6]. Aim of these approachesis to produceschematics with transistor sizes and component values accounting for high level performance and process specifications. Unfortunately, some performances such as phase margin and bandwidth are strongly influenced by circuit parasitics, which can be evaluated ....
R. Harjani, R. A. Rutenbar and L. R. Carley, "Analog Circuit Synthesis for Performance in OASYS", in Proc. ICCAD, pp. 492--495, November 1988.
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