J. L. Turley. Thumb squeezes ARM code size. Microprocessor Report, 9(4), Mar. 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....As a secondary effect, we also expect some performance benefits from the improved cache performance. We do not want to introduce a short instruction coding that results in less powerful instructions so that more instructions are dynamically executed like in the ARM Thumb instruction set [16]. Therefore, we have been careful to keep all original RISC instructions in the ISA. This gives the compiler the possibility to choose between short and original instructions during code generation. As baseline ISA, we have used the MIPS like PISA used in the SimpleScalar computer system ....

....However, in the literature there also exist several attempts and approaches to both compact the code and to utilize instructions of variable length in RISC machines. The most widely known approaches to reduce the length of RISC style instructions are the ARM Thumb and the MIPS16 instruction sets [10, 16]. Both Thumb and MIPS16 are pure subsets of the normal ARM and MIPS instruction sets using 16 bit instead of 32 bit instructions. This is possible through restrictions in the usage of the register set and of addressing modes as compared to the original 32 bit instruction sets. The usage of mixed ....

J. L. Turley, Thumb Squeezes ARM code size, Microprocessor Report, 9(4), pp. 1-5, 27 March 1995.

....class les. This work di ers from ours since decompression must be performed before execution. The work of Rayside et al. 24] also applies to class les, but these techniques does not apply to the bytecode itself. Hoogerbrugge et al. 9] uses a similar strategy of the Thumb and MIPS16 processors [27, 13] to compress some parts of the program. But instead of applying compression on the binary executable, they automatically generate a tailored virtual machine for the intermediate form of the C program. When the intermediate form is translated into a virtual program, frequent sequences of virtual ....

J. L. Turley. Thumb squeezes ARM code size. Microprocessor Report, 9(4), March 1995.

....bit in the processor selects the current instruction set used to decode instructions. This allows a program to have the advantages of wide, expressive instructions for high performance and short instructions for code density. ARM and MIPS are examples of such dual mode instruction sets. Thumb [ARM95, Turley95] and MIPS 16 [Kissell97] are defined as the 16 bit instruction set subsets of the ARM and MIPS III architectures. A wide range of applications were analyzed to determine the composition of the subsets. The instructions included in the subsets are either frequently used, do not require a full ....

J. L. Turley, "Thumb squeezes arm code size", Microprocessor Report, 9(4), pp. 1-5, 27 March 1995.

....level which brings more opportunity for compaction. They obtain an average 78 factor of compression. Hoogerbrugge et al. 10] have very good results in producing compact code and in spirit it is one of the closest work to ours. It is similar to the ideas found in the Thumb and MIPS16 processors [21, 13] where only a part of the program is compressed. It gives a faster execution by compressing only the less used parts. A tailored VM is automatically generated given a C program. They obtain a 70 factor of compression when comparing the native codes. Closer to Scheme, Scheme 48[11] is a compact ....

J. L. Turley. Thumb squeezes ARM code size. Microprocessor Report, 9(4), March 1995.

....level which brings more opportunity for compaction. They obtain an average 78 factor of compression. Hoogerbrugge et al. 11] have very good results in producing compact code and in spirit it is one of the closest work to ours. It is similar to the ideas found in the Thumb and MIPS16 processors [22, 14] where only a part of the program is compressed. It gives a faster execution by compressing only the less used parts. A tailored VM is automatically generated given a C program. They obtain a 70 factor of compression when comparing the native codes. Closer to Scheme, Scheme 48[12] is a compact ....

J. L. Turley. Thumb squeezes ARM code size. Microprocessor Report, 9(4), March 1995.

....that most applications have a small critical part where most of the execution time is spent, several recently introduced processors have been designed with two execution modes: one for high code density and one for high execution speed. Examples of these dual mode processors are the ARM Thumb [2] and the MIPS16 [3] If only a small part of an application is performance critical, a dual mode processor can achieve the code size of a processor designed for high code density, and the performance of a processor designed for high execution speed. An alternative for dual mode processors is a ....

J. L. Turley, `Thumb squeezes ARM code size', Microprocessor Report, 9(4), (1995).

....to conventional native instruction programs, the techniques used provide some of the smallest program representations. 2.1 Improved encodings for native instructions Although a RISC instruction set is easy to decode, its fixed length instruction formats are wasteful of program memory. Thumb [ARM95, Turley95] and MIPS 16 [Kissell97] are two recently proposed instruction set modifications which define reduced instruction word sizes in an effort to reduce the overall size of compiled programs. Thumb and MIPS 16 are defined as subsets of the ARM and MIPS III architectures. A wide range of applications ....

J. L. Turley. Thumb squeezes arm code size. Microprocessor Report, 9(4), 27 March 1995.

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J. L. Turley. Thumb squeezes ARM code size. Microprocessor Report, 9(4), Mar. 1995.

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J. L. Turley. Thumb squeezes ARM code size. Microprocessor Report, 9(4), Mar. 1995. 40

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J. Turley. Thumb squeezes ARM code size. Microprocessor Report, 9(4):1--5, Mar. 1995.

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