S.Sutarwala, P.Paulin, Y.Kumar, Insulin: An Instruction Set Simulation Environment, in Proc. of CHDL'93, pp355-362, Ottawa, Canada, April 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....will be obtained from a VHDL or ESTEREL front end. The internal representation of CFSM (SHIFT) is suitable for preliminary analysis by formal verification techniques. The research area concerning hardware software co simulation has been widely explored for DSP oriented applications only [Buc94] [Sut93]. A survey of alternative strategies for more general applications is presented in [Alt91] and [Vah95b] while [Wol94] provides an extensive survey of the existing open research issues and project on embedded system co design. A specific approach is 4 proposed in [Gup92] through the Poseidon ....

....the operation according to the target CPU. Up to now, according to the most common types of embedded system microprocessors, effects concerning pipelined instruction execution or parallel fetch have not been considered. For an analysis on how these issues can be managed for DSP applications, see [Sut93]. During software synthesis, processes as well as the operating system microkernel are directly assembled into VIS code. As reported above, the software system is composed of processes and of a kernel basically operating as a context switcher: although no sophisticated mechanisms for memory ....

S.Sutarwala, P.Paulin, Y.Kumar, Insulin: An Instruction Set Simulation Environment, in Proc. of CHDL'93, pp355-362, Ottawa, Canada, April 1993.

....SLED does not contain enough information about the machine to allow simulator generation. LISA has been used primarily to generate a cycle accurate simulator [9] whose main characteristic is a behavioral model of the pipeline. The FLEXWARE system contains the CODESYN code generator and the Insulin[20] simulator. The simulator uses a VHDL model of a generic parameterizable machine. The application is translated from the user defined target instruction set to the instruction set of this generic machine. The Trimaran[23] system uses MDes to retarget the compiler back end. However, it allows only ....

S. Sutarwala, P. G. Paulin, and Y. Kumar. Insulin: An instruction set simulation environment. In Proc. CHDL, April 1993.

....However, SLED does not contain semantic information needed for simulator generation. LISA has been used primarily to generate a cycle accurate simulator [3] whose main characteristic is a behavioral model of the pipeline. The FLEXWARE system contains the CODESYN code generator and the Insulin[15] simulator. The simulator uses a VHDL model of a generic parameterizable machine. The application is translated from the user defined target instruction set to the instruction set of this generic machine. The Trimaran[17] system uses MDes to retarget the compiler backend. However, it allows only a ....

S. Sutarwala, P. G. Paulin, and Y. Kumar. Insulin: An instruction set simulation environment. In Proc. CHDL, April 1993.

....performed after instruction selection) whereas Aviv addresses them concurrently in order to find a globally optimized solution. 2.2.2 FlexWare FlexWare [46] is a software firmware development environment for ASIPs and commercial processors. It is composed of an instruction set simulator, Insulin [52], and a retargetable code generator, CodeSyn [45] Insulin provides a cycle true VHDLbased simulation environment. CodeSyn takes an algorithm written in a high level language and maps it into the target instruction set to produce optimized machine code for ASIPs and commercial processor cores. ....

S. Sutarwala, P. Paulin, and Y. Kumar. Insulin: An instruction set simulation environment. In Proceedings of the 1993 Conference on Hardware Description Languages, pages 355--362, 1993.

....set simulators use the interpretive simulation technique. Their main disadvantages are the low simulation speed (2K 20K insns s [2] and their inability to be extended by the user. Instruction set simulators are standard components of HW SW, and processor compiler co design environments [1,3,4]. The speed of these simulators ranges from 300 insns s to 20K insns s depending on the character of the processor model, the simulation technique applied or the accuracy level provided. The compiled simulation technique we use for our simulator is well known in simulation of hardware circuits, ....

S. Sutarwala, et al., "Insulin: An instruction set simulation environment," in Proc. of CHDL-93, Ottawa, Canada, pp. 355--362, 1993.

....the delay for the result to become available. VHDL [18, 2] is a standardized language with considerable semantic richness. Therefore, several description styles are used. However, if different tools support different styles or language subsets, the benefits of the standardization vanish. Insulin [25] is an instruction set simulator for application specific pro 4 Chapter 1 cessors and is based on a reconfigurable VHDL model of a generic instruction set processor . Basically, a library of primitive operations is provided of which the simulation functions for the target processor can be ....

S. Sutarwala, P.G. Paulin, Y. Kumar, "Insulin: An Instruction Set Simulation Environment", in Proc. ???? CHDL-93, 1993, pp. ???--??? 18 Chapter 1

....are the main design topics. Table 1. Some references on different fields of ES design. The references are grouped according their main focus of interest. Topics References Specification, Verification ASAR [6] A.Benveniste, G. Berry [9] Codes [12] Cosmos [42] 49] Simulation Insulin [105]; Ptolemy [13] 53] J.A. Rowson [93] B. Kerridge [56] Code Generation Capsys [5] Chess [58] CodeSyn [64] C. Monahan, F. Brewster [70] MOVE [36] Oscar [57] PEAS 1 [2] Analysis ADAM [48] X. Hu [37] J. Gong, et al. 29] Partitioning Cosyma [21] 34] A. Kalavade , E.A. Lee [54] K.A. ....

.... compiler of the MOVE system [17] 36] 4 A special problem for video processing are the high simulation times [1] This can be avoided in part by a structured top down approach which reduces the number of simulations at a low level, and in addition, fast instruction set simulators like Insulin [105], or the simulator of the MOVE system [36] among others, can be used. A case study using a system level approach for designing a JPEG chip was carried out for the USC [30] system. The generated system consists of three chips for implementing the DCT (Discrete Cosine Transform) the IDCT (Inverse ....

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S. Sutarwala, P.G. Paulin, and Y. Kumar. Insulin: An instruction set simulation environment. In Proc. CHDL, pages 355--362, Ottawa, Canada, April 1993.

....to focus our study on retargetable development tools for DSP processors, but evaluate them for microprocessors as well. Several approaches have been taken to the problem of retargetable DSP processor models. The FlexWare tools set [1] included a retargetable instruction set model called Insulin [1, 2]. Insulin was built around a partially reconfigurable VHDL simulation model of a generic processor. It could be reconfigured for bit width, number of registers, number of ALUs, etc. Insulin cross assembled target processor instructions into micro instructions for the generic processor, which were ....

S. Sutarwala, P. Paulin, Y Kumar, "Insulin: An Instruction Set Simulation Environment", Proc. of CHDL, Ottawa, Canada, April 1993, pp. 355-362

....supports the rapid development of cycle true behavioural models of a target instruction set that can be co simulated with other hardware models. This section describes the features and basic principles of the Insulin system. A detailed description of specific aspects of the system can be found in [SuPK93] SuPa94] Paul95b] As shown in Slide 48, there are three main components to the Insulin environment: 1. A partially reconfigurable VHDL simulation model of a generic processor. This is the core of the Insulin toolset. 2. A cross assembler that converts the user s target assembly code to the ....

....nature of the model and displays results in terms of the user s instruction set specification and syntax. It allows the user to perform step by step debugging, set break points, as well as view and modify the register and memory contents. For details and an illustration of the interface, see [SuPK93] 6.3 Retargetable Compilation The FlexWare retargetable compiler environment used at ST relies on two main approaches: 1. A model based approach, as described in [Paul95b] DRAFT: NATO Advanced Study Institue on Hardware Software Codesign, Lake Como, Italy, June 1995 Trends in Embedded ....

S. Sutarwala, P. G. Paulin, Y. Kumar, "Insulin: An Instruction-Set Simulation Environment", Proc. of Computer Hardware Description Language (CHDL) Conference, Ottawa, Canada, Apr. 1993, pp. 355-362.

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S. Sutarwala, P. Paulin, and Y. Kumar. Insulin: An Instruction Set Simulation Environment. Proceedings of CHDL-93, Ottawa, Canada, 1993.

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