A. Yeung and J. Rabaey, "A data-driven architecture for rapid prototyping of high throughput DSP algorithms," in Proc. IEEE VLSI Signal Processing Workshop, 1992, pp. 225--234. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1998) (1 citation) Self-citation (Rabaey) (Correct)
....for HBISR, but also for relatively minor alterations in the chip functionality as is often required in modern day designs. An off chip controller can be replaced as necessary since it is located on a separate chip. A number of high performance datapath intensive chips have used this option (e.g. [18]) The same drawbacks and advantage as with the programmable controller hold. The composed controller is located on chip, and is the composition of all possible control configurations that may be used. Its effectiveness depends on how well several different (but often similar) controllers can be ....
A. Yeung and J. Rabaey, "A data-driven architecture for rapid prototyping of high throughput DSP algorithms," in Proc. IEEE VLSI Signal Processing Workshop, 1992, pp. 225--234.
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1993) (1 citation) Self-citation (Rabaey) (Correct)
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A. Yeung and J. Rabaey, "A Data-Driven Architecture for Rapid Prototyping of High Throughput DSP Algorithms, " IEEE VLSI Signal Processing Workshop, pp. 225-234, 1992.
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