J. P. Hayes, "On modifying logic networks to improve their diagnosability, " IEEE Trans. Comput., vol. C-23, pp. 56--62, Jan. 1974. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
On-Line Fault Detection for Bus-Based Field.. - Shnidman.. (1998) (9 citations) (Correct)
....addresses the needs of the last two types of functional faults. After the FPGA design is configured, the only relevant faults are the stuckat faults which may occur as the consequence of particle radiation. Therefore, our in field testing focuses on stuckat faults. Single event upset (SEU) 9] [10] faults are also captured by the approach. Even though the majority of the FPGA area is taken up by interconnect, it is reasonable to focus the fault detection system on the LUT s and flip flops. These structures hold the programmable components of the device, and are much more likely to ....
J. P. Hayes, "On modifying logic networks to improve their diagnosability, " IEEE Trans. Comput., vol. C-23, pp. 56--62, Jan. 1974.
A Minimal Universal Test Set for Self-Test of.. - Ugur Kalay Douglas (1998) (Correct)
....x 1 x 2 x n f AND Part Literal Part c 2 . c 2 c 1 o 2 Linear Part Check Part . o 1 A c 1 B Figure 4: Easily testable ESOP circuit. Hayes used mainly EXOR gates as additional circuitry to make a logic circuit easily testable [9]. Likewise, in our realization, we mainly use EXOR gates in the additional circuitry to take advantage of the superior testability properties of the EXOR gate. This allows us to obtain a minimal and universal test set. 3.2 The Fault Model A fault model represents failures that affect functional ....
J. P. Hayes, "On modifying logic networks to improve their diagnosability," IEEE Trans. on Comp., vol. C-23, no. 1, pp. 56--62, 1974.
On-line Fault Detection for Programmable Logic - Shnidman, Mangione-Smith.. (Correct)
....are presented in Section 6. Some concluding remarks are given in Section 7. 2. PRELIMINARIES The assumptions used in implementing the fault scanning system will be discussed here. The types of faults addressed by this system are the Single Stuck Fault (SSF) 6] and the Single Event Upset (SEU) [6, 7]. This fault model is sufficient to verify LUTs and flip flops. While the current design of the system does not yet address faults in the interconnect and control paths, other schemes have been proposed which address such faults [8 10] It is reasonable to focus the current fault detection system ....
J. P. Hayes, "On Modifying Logic Networks to Improve Their Diagnosability," IEEE Transactions on Computers, vol. 23, pp. 56-62, 1974.
Behavioral-Level Synthesis of Heterogeneous BISR.. - Guerra, Potkonjak.. (1993) (1 citation) (Correct)
.... to improve manufacturability, any off line testing and diagnosis scheme can be used (i.e. partial scan sequential automatic test pattern generation (ATPG) Che90, Lee90, Nie91] full scan and combinational ATPG [Eic78] Built In Self Test (BIST) Wil73, Bar87] and insertion point based schemes [Hay74]) Note that any scheme which does not have strong diagnosis capabilities (e.g. IDDQ based testing [Gul93] cannot be used. If the BISR methodology supports in field reconfiguration after failure of particular hardware part(s) a BIST scheme is required. In this case, testing capabilities are ....
J.P. Hayes, "On Modifying Logic Networks to Improve their Diagnosability," IEEE Transactions on Computers, Vol. 23, No. 1, pp. 56-62, 1974.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC