Vicki H. Allan, Reese B. Jones, Randal M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, September 1995. Home/Search Document Details and Download
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Time-Constrained Failure Diagnosis in Distributed Embedded .. - Nagarajan Kandasamy John (2002) (Correct)
....buffering also decouples the various task sets, allowing them to be pipelined. For example, a new iteration of the actuatorcontrol function may now execute concurrently with the on going diagnosis of previous iterations. Functional pipelining approaches fall into the following two broad categories [14]: Graph unrolling: The original graph is replicated to expose tasks across multiple iterations which are then overlapped to obtain the schedule. However, this method introduces jitter or timing variations between successive executions of control tasks. Graph folding: Tasks belonging to a single ....
V. H. Allan et al., "Software Pipelining," ACM Computing Surveys, vol. 27, no. 3, pp. 367-432, Sep. 1995.
SIRA: Schedule Independent Register Allocation for Software - Pipelining Sid Ahmed (Correct)
....as follows : next section introduces a motivating example, then we formalize the problem. Finally we give a formulation with linear integer programming techniques and conclude with related work. For every detail about loop software pipelining and cyclic register allocation, one can refer to [AJLA95, WEJS94, ELM95]. 2 Motivating Example Let us consider the following loop with two instructions u and v. for i=1; i =n; i u A(i 3) v . A(i) There is a flow dependency between u and v with distance = 3. This means that the operation v reads the value produced by u ....
Vicki H. Allan, Reese B. Jones, Randall M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367-- 432, 1995.
A Flow Graph Formulation of Optimal Software Pipelining - Fimmel, Müller (2002) (Correct)
....allows to operate more units in parallel. These developments raise the challenge to maximally exploit available resources, and to find operating schedules with minimum latencies. Current compilers, using heuristics for resource exploitation and loop scheduling, offer good solutions to these tasks [1, 18]. However, for the production of program libraries and for computationally intensive algorithms, the best solutions are needed, even if the compilation may take longer than with heuristic approaches. This substantiates the use of Integer Linear Programming formulations [2, 4, 12, 13, 14] which ....
V. Allan, R. Jones, R. Lee, and S. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, September 1995.
MIRS : Modulo Scheduling with Integrated Register Spilling - Zalamea, Llosa, Ayguadé.. (Correct)
....supporting increasing levels of instruction level parallelism (ILP) Software pipelining [11] is an instruction scheduling technique able to exploit this ILP out of a loop by overlapping operations from various successive loop iterations. Different approaches have been proposed in the literature [2] for the generation of software pipelined schedules. Some of them mainly focus on achieving high throughput [1, 13, 18, 25, 26, 28] This work has been supported by the Ministry of Education of Spain under contract TIC 98 511, and by CEPBA (European Center for Parallelism of Barcelona) Javier ....
V. Allan, R. Jones, R. Lee, and S. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, September 1995.
Software Bubbles: Using Predication to Compensate.. - Goldberg, Chapman, .. (2002) (Correct)
....the value of the variable k is 2. Since # and , for every three iteration slots in the original pipeline, only two slots should be enabled. This leads to the bubbling situation illustrated in figure 3(a) The desired predication pattern is achieved by using predication registers, say p[1] through p[L] where the kernel operations from the th iteration slot are predicated on mod ( Initially, the first predicate registers are set to 1 and the remaining predicate registers to 0. Upon each execution of the pipeline kernel, the predication pattern rotates, ....
....registers is accomplished depends on whether the machine supports rotating predicate registers or not. If so, then the only extra operation that must be inserted into the kernel is p[0] move p[ The next time the kernel is executed (i.e. after the rotating register base is decremented) p[1] will contain the value of p[ from the previous kernel, which gives the desired rotating behavior. If the machine does not support rotating predicate registers, an explicit shift of the aggregate predicate register is necessary. p0 = move p PR = shl PR,1 The shift operation should be ....
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V. Allan, R. Jones, R. Lee, and S. Allan. Software pipelining. ACM Computing Surveys, 27(3), 1995.
Software Bubbles: Using Predication to Compensate for.. - Goldberg, Crutcher, al. (2002) (Correct)
....the value of the variable k is 2. Since # # # and # # #,for every three iteration slots in the original pipeline, only two slots should be enabled. This leads to the bubbling situation illustrated in figure 3(a) The desired predication pattern is achieved by using # predication registers, say p[1] through p[L] where the kernel operations from the #th iteration slot are predicated on ##### ### mod #####. Initially, the first # predicate registers are set to 1 and the remaining predicate registers to 0. Upon each execution of the pipeline kernel, the predication pattern rotates, as we saw ....
....registers is accomplished depends on whether the machine supports rotating predicate registers or not. If so, then the only extra operation that must be inserted into the kernel is p[0] move p[#] The next time the kernel is executed (i.e. after the rotating register base is decremented) p[1] will contain the value of p[#] from the previous kernel, which gives the desired rotating behavior. If the machine does not support rotating predicate registers, an explicit shift of the aggregate predicate register is necessary. p0 = move p# PR = shl PR,1 The shift operation should be ....
[Article contains additional citation context not shown here]
V. Allan, R. Jones, R. Lee, and S. Allan. Software pipelining. ACM Computing Surveys, 27(3), 1995.
Register Allocation for Software Pipelining with.. - Itoga, Haraikawa.. (2001) (Correct)
....register by the overlapped variables. The register allocation experiments using pseudo loop programs shows that the strategies are effective on sharing. Keywords software pipelining, conditional branches, predication, register allocation, rotating register. INTRODUCTION Software pipelining[1] has been shown as an effective technique for scheduling loop intensive programs of VLIW and super scalar processors. Modern processors, like IA 64 architecture, have hardware faculties supporting the technique. Register rotation and predication are these faculties on IA 64 architecture[2] ....
Vicki. H. Allan, Reese B. Jones, Randall M. Lee, Stephen J. Allan: "Software Pipelining," ACM Computing Surveys, Vol. 27, No. 3, pp. 367--432, Sep 1995.
Register Allocation for Predicated Pipelining - Using Spiral Graph (2002) (Correct)
....gap increases between the operations # H. Itoga is now with Ibaraki Industrial Technology Center, Ibaraki, Japan. and memory references. Register allocation is also more complex since some modern processors have special hardware facilities, such as register renaming[1] Software pipelining[2] is an optimization method for loop intensive programs using Instruction Level Parallelism (ILP) It schedules the instructions in the iterations in order to overlap partially on the compilation time. Two software pipelining problems have been solved by hardware support: one was that the lifetimes ....
Vicki H. Allan, Reese B. Jones, Randall M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, Sep 1995.
Spatial Computation - Mihai Budiu Girish (2004) (Correct)
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Vicki H. Allan, Reese B. Jones, Randal M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, September 1995.
Loop Fusion for Clustered VLIW Architectures - Yi Qian Science (Correct)
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V. Allan, R. Jones, R. Lee, and S. Allan. Software Pipelining. ACM Computing Surveys, 27(3), September 1995.
Loop Transformations for Architectures with Partitioned.. - Huang, Carr, al. (2001) (Correct)
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V. Allan, R. Jones, R. Lee, and S. Allan. Software Pipelining. ACM Computing Surveys, 27(3), September 1995.
Low-cost Register-pressure Prediction for Scalar Replacement.. - Ma, Carr, Ge (Correct)
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V. Allan, R. Jones, and R.Lee. Software pipelining. ACM Computing Surveys, 7(3), 1995.
Register Assignment for Software Pipelining with Partitioned .. - Jason Hiser Steve (2000) (Correct)
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V. Allan, R. Jones, R. Lee, and S. Allan. Software Pipelining. ACM Computing Surveys, 27(3), September 1995.
Improving Software Pipelining By Hiding Memory Latency With.. - Bedy, al. (Correct)
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V.H. Allan, R. Jones, R. Lee, and S.J. Allan. Software Pipelining. ACM Computing Surveys, 27(3), September 1995.
Improving Software Pipelining with Hardware Support for.. - Carr, Sweany (1998) (Correct)
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V. Allan, R. Jones, R. Lee, and S. Allan. Software Pipelining. ACM Computing Surveys, 27(3), September 1995.
Spatial Computation - Budiu, Venkataramani, Chelcea.. (2004) (Correct)
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Vicki H. Allan, Reese B. Jones, Randal M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, September 1995.
Loop Shifting for Loop Compaction - Alain Darte And (2000) (1 citation) (Correct)
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Vicki H. Allan, Reese B. Jones, Randall M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367432, September 1995.
Super Scalar Sample Sort - Sanders, Winkel (2004) (1 citation) (Correct)
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V.H. Allan, R.B. Jones, R.M. Lee, and S.J. Allan. Software Pipelining. Computing Surveys, 27(3):367--432, September 1995.
Loop Shifting for Loop Compaction - Darte, Huard (1999) (1 citation) (Correct)
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Vicki H. Allan, Reese B. Jones, Randall M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367432, September 1995.
Creating converged Trace Schedules Using String Matching - Narayanasamy, Hu, Sair.. (2004) (Correct)
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V. H. Allan, R. B. Jones, R. M. Lee, and S. J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, 1995.
Reduced Code Size Modulo Scheduling in the Absence of.. - Llosa, Freudenberger (2002) (1 citation) (Correct)
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V. Allan, R. Jones, R. Lee, and S. Allan. Software pipelining. ACM Computing Surveys 27,3 (Sept. 1995), pp. 367-432.
Spatial Computation - Budiu (2003) (Correct)
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Vicki H. Allan, Reese B. Jones, Randal M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, September 1995.
Unknown - (Correct)
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V. Allan, R. Jones, R. Lee, and S. Allan. Software Pipelining. ACM Computing Surveys, 27(3):367--432, 1995.
SIRA: Schedule Independent Register Allocation for Software.. - Touati, Eisenbeis (2001) (Correct)
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Vicki H. Allan, Reese B. Jones, Randall M. Lee, and Stephen J. Allan. Software pipelining. ACM Computing Surveys, 27(3):367-- 432, 1995.
MIRS: Modulo Scheduling with Integrated Register Spilling - Zalamea, Llosa.. (Correct)
No context found.
V. Allan, R. Jones, R. Lee, and S. Allan. Software pipelining. ACM Computing Surveys, 27(3):367--432, September 1995.
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