H.R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....low complexity approximations of the sub circuits to be used as inputs for the rest of the system. Some preliminary results of this methodology are reported. 1 Introduction It is well known that timed automata (TA) AD94] are well suited for modeling delays in digital circuits [D89,L89,MP95] Although some applications of TA technology for solving timing related problems for such circuits have been reported [MY96,BMPY97,TKB97,TKY 98,BMT99,BJMY02] the state and clock explosion associated with such models, restricted the applicability of TA to small circuits. In this work we ....

H.R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.

....results for the usage of refinement mappings to prove properties of non timing based algorithms were proved in [1] and [20] There has been some prior work on using asserttonal reasoning to prove timing properties. In par ticular, naase [6] Shankar and Lam [24] Tel [27] Schneider [23] Lewis [12] and Shaw [25] have all de veloped models for timing based systems that incorporate time information into the state, and have used invariant assertions to prove timing properties. In [27] and [12] in fact, the information that is included is similar to ours in that it is also predictive timing ....

....timing properties. In par ticular, naase [6] Shankar and Lam [24] Tel [27] Schneider [23] Lewis [12] and Shaw [25] have all de veloped models for timing based systems that incorporate time information into the state, and have used invariant assertions to prove timing properties. In [27] and [12], in fact, the information that is included is similar to ours in that it is also predictive timing information (but not exactly the same information as ours) None of this work has been based on mappings, however. Several other, quite different formal approaches to proving timing properties have ....

H. lq,. Lewis, "Finite-State Analysis of Asyn- chronous Circuits with Bounded Temporal Uncertainty, " Technical Report TR-15-89, Aiken Computation Laboratory, Harvard University.

....ordering of the fractional values of the clocks are equivalent. Although this approach eliminates the need to discretize time, the state space can explode if the delay ranges are large. Another approach to continuous time is to represent the equivalence classes as convex polyhedra called zones [33, 15, 47, 2]. The zones are represented by sets of linear inequalities (also know as di erence bound matrices or DBMs) Although its worst complexity is worse than the discrete time or region approaches, the zone approach often generates larger equivalence classes resulting in smaller state spaces when ....

Lewis, H. R. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Tech. rep., Harvard University, July 1989.

....sucient to enable it has red. This approach requires that the timing information contains both a set of red rules, R f , and information about the time relationships between the rules currently in Rm . These time relationships are represented with geometric regions, which were rst introduced in [9, 10, 11]. This approach has been shown to be ecient for timed state space exploration [12, 8, 13] When the geometric region approach is used for timing analysis, a constraint matrix M speci es the maximum di erence in time between the enabling times of all the currently enabled rules. The 0th row and ....

H. R. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical report, Harvard University, July 1989.

....of timed states is dependent on the size of the delay ranges and the number of concurrently enabled clocks which can quickly explode for even relatively small systems. Another approach to continuous time is to represent the equivalence classes as convex geometric regions (or zones) 7] 8] [9]. These geometric regions can be represented by sets of linear inequalities (also known as difference bound matrices or DBMs) These larger equivalence classes can often result in smaller state spaces than those generated by the unit cube approach. While geometric methods are efficient for some ....

H. R. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical report, Harvard University, July 1989.

....central clock period and the skew between the receiver and transmitter. We model the uncertainty concerning the delay associated with gates using the bi bounded delay model, that is, we associate with every gate an interval [l; u] indicating the lower and upper bounds for its switching delay (see [L89] BS94] MP95] and [AMP98] for the exact definitions) Following [MP95] we can model any logical gate with a delay [l; u] using a timed automaton with 4 states (0 stable, 0 excited, 1 stable and 1 excited) and one clock. In particular, each stage of STARI is modeled by the three timed automata ....

H.R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.

....rising and falling (which are the discrete events) of the digital signals. The lower bound is a positive constant, such that any cycle in the model takes at least k time units to complete, for some positive constant k, and so, the automata are progressive; 8 A. V. Moura and G. A. Pinto see also [6] where this same discussion occurs in a similar formalism. It is worth noting that the progress requirement does not nullify the dense time assumption. In fact, one of the results in [3] is that cyclic circuits in that model, in general, do not admit discretization. We can show that when the ....

H. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical Report TR-15-89, Harvard Univ., 1989.

....18 A. V. Moura and G. A. Pinto expressiveness power of nondeterministic timed automata to specify properties as long as the process satis es this assumption. This assumption is commonly adopted in an important application of real time veri cation techniques: the analysis of digital circuits [14, 6, 15]. For instance, in [6, 15] a timed automaton model for asynchronous circuits is proposed. Every logical gate is followed by a delay element constraining, between lower and upper bounds, the rising and falling (which are the discrete events) of the digital signals. The lower bound is a positive ....

....Our construction gives a semi decision procedure, which is guaranteed to nish, for instance, when there is a bound on the number of events that the process can generated in a nite interval of time. This assumption is frequently adopted in practical applications of veri cations techniques [14, 6, 15]. Hence, the very expressive formalism of nondeterministic timed automata can be used to specify properties for these probabilistic processes. The method is quite expensive, as can be seen in the bound on the number of equivalence classes with K generic clocks in Section 4.1. In particular, it is ....

H. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical Report TR-15-89, Harvard Univ., 1989.

....equivalent. Although this approach eliminates the need to discretize time its complexity of O(jSj n ln 2 ( k ln 2 ) n 4 (1=k) is much worse than discrete time and the state space using this method typically explodes if the delay ranges are large. Dill [28] Berthomieu [12] Lewis [42], and Alur [3] present another approach to continuous time where the equivalence classes are represented as convex geometric regions (or zones) Geometric regions can be represented by sets of linear inequalities (also known as difference bound matrices or DBMs) The worst case complexity of this ....

Lewis, H. R. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Tech. rep., Harvard University, July 1989. 146

....clock period and the skew between the receiver and transmitter. We model the uncertainty concerning the delay associated with gates using the bi bounded delay model, that is, we associate with every gate an interval [l; u] indicating the lower and upper bounds for its switching delay (see [L89] BS94] MP95] and [AMP98] for the exact definitions) Following [MP95] we can model any logical gate with a delay [l; u] using a timed automaton with 4 states (0 stable, 0 excited, 1 stable and 1 excited) and one clock. In particular, each stage of STARI is modeled by the three timed ....

H.R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.

....has stabilized until the next time their values are sampled. When one is not satisfied with the type of answers suggested by the abstract untimed models or with the performance of clocked systems, timed models seem to be the next logical step (see also [BS94] It has been shown elsewhere ( D89] L89] MP95] how a very general model of non clocked circuits with delays can be translated into timed automata, on which one can ask all sorts of interesting timing questions ( ACD93] HNSY94] AMP95] The only problem with these models is the amount of time (and space) that might elapse between ....

H.R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.

....Another approach to represent timed states is to use convex geometric regions (or zones) as shown in Figure 7(c) Even though the worst case performance is much worse than either the unit cube or the discrete time approaches, this approach usually performs well in practice. Dill [17] Lewis [18], and Berthomieu and Diaz [19] originated geometric timing, and it has become an active area of research [20] 21] 22] Unfortunately, as illustrated later, for highly concurrent systems, geometric methods alone can result in a substantial state explosion. A number of techniques have been ....

H. R. Lewis, "Finite-state analysis of asynchronous circuits with bounded temporal uncertainty," Tech. Rep., Harvard University, July 1989.

....the continuous model [6, 14] This does make the state space finite, but it still explodes, especially if the delay ranges are large [15] All of the timing analysis algorithms presented here are based on geometric regions. Geometric regions are a good way to concisely represent timing information [4, 8, 2, 14]. Large numbers of discrete timed states can often be condensed into a single contiguous geometric region that contains all of them, producing a large reduction in the number of timed states generated [14] While worst case behavior of geometric timing is actually worse than the discrete method it ....

H. R. Lewis. Finite-state analysis of asynchronous circuits with boundedtemporal uncertainty. Technicalreport, Harvard University, July 1989.

....defined to be Rm Theta s c Theta TI. A timed state contains all the information necessary to compute the set of satisfied rules, R s . Only rules in R s are allowed to fire and cause a transition to another state. Our timing information is represented with geometric regions, first introduced in [22, 23, 24]. This approach has been shown to be efficient for timed state space exploration [25, 26, 18] and can be easily modified to analyze TEL structures without any substantial increase in synthesis time. The geometric region based timing analysis method for timed ER structures is based on keeping track ....

H. R. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical report, Harvard University, July 1989.

....equivalent. Although this approach eliminates the need to discretize time, the number of timed states is dependent on the size of the delay ranges and can explode if they are large. Another approach to continuous time is to represent the equivalence classes as convex geometric regions (or zones) [7 9]. These geometric regions can be represented by sets of linear inequalities (also known as difference bound matrices or DBMs) These larger equivalence classes can often result in smaller state spaces than those generated by the unit cube approach. While geometric methods are efficient for some ....

H. R. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical report, Harvard University, July 1989.

....the transition times of the local clocks is also modeled but not shown. It takes less than five seconds to explore the state space of this model using the POSET state space algorithm on a 400MHz Pentium II. For comparison the model is also analyzed using the standard, geometric region based method [9, 19, 10]. This method requires 196 seconds to analyze the model. The iteration time provided by the POSet al..gorithm makes it reasonable to iteratively adjust the Celldelay values, global clock speed, and local clock timings to determine the working ranges of the circuit under a variety of assumptions. The ....

H. R. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical report, Harvard University, July 1989.

....at most (k 1) time units. Consequently, it is impossible to state precisely certain simple requirements on the delays such as the delay between two transitions equals 2 seconds. The third approach to modeling real time behavior models time, more realistically, as a continuous quantity (e.g. [25, 29, 27, 14]) We prefer to use this dense time model (see [2] for some advantages of the dense time model over the discrete models) With each transition we associate a time value chosen from the set of nonnegative reals R. We regard computations as continuous trees, in which the paths are maps from the ....

....and event based, whereas the semantics of timed graphs is branching time and state based. An automata theoretic approach to verification of timing requirements of real time systems has been developed using timed automata [4] A model similar to ours was independently proposed and studied by Lewis [27]. He defines state diagrams, and gives a way of translating a circuit description to a statediagram. A state diagram is a finite state machine where every edge is annotated with a matrix of intervals constraining various delays. Both the formalisms, state diagrams and timed graphs, have the same ....

H. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical Report TR-15-89, Harvard University, 1989.

....These variables may take on any one of the following values: 0 denotes a stable low signal, R denotes a signal enabled to rise, 1 denotes a stable high signal, and F denotes a signal enabled to fall. The timing information, T I, is represented with geometric regions, which were first introduced in [5, 19, 24]. When the geometric region approach is used for timing analysis, a constraint matrix M specifies the maximum difference in time between the enabling times of all the currently enabled rules. The 0th row and column of the matrix contain the separations between the enabling times of each enabled ....

Lewis, H. R. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Tech. rep., Harvard University, July 1989. 52

....b ,ca ,c aa ,ca cc d d [2,inf]c [4,10]b [4,10]b [2,inf]c cc d d (a) b) c) Fig. 1. a) A fast NAND gate with inputs a and b and output c, b) a delay buffer with input c and output d, and (c) with timing requirements annotated b for behavior and c for constraint. Dill [6] Lewis [7], and Berthomieu and Diaz [8] originated geometric state space exploration, and it has become an active area of research [9, 10, 11] We improve these techniques for systems with concurrency using partial orders and apply them to circuit verification. Recent work by Yoneda et al. 12] also ....

....discrete states can be astronomical. 4 Geometric Timing Verification In this section, we discuss a known time verification technique, geometric timing, that usually performs well in practice, even though the worst case performance is much worse than either the discrete or the unit cube approaches [6, 7, 8, 9, 10, 11]. 4.1 Geometric Regions Rather than consider at each step a single discrete timed state, or a minimum equivalence class of timed states, the geometric timing method considers a large number of timed states in parallel. Specifically, convex geometric regions of timed states represented by upper ....

Harry R. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical report, Harvard University, July 1989.

....conditions or in the delay parameters of the gates, without any problem. This is because the simulation is global in the sense that instead of simulating one possible execution of the circuit, we simulate in one step an infinite (and even uncountable) number of executions (see also [BM83] L89] D89] BD91] AD94] for the origins of this geometric simulation method for timed systems, and [ACH 95] AMP95 a] for the application of this approach in the more general setting of hybrid systems) The core of this paper is a careful translation of circuits, defined via a system of ....

H.R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.

....synthesis and verification techniques. In this section, we first discuss geometric timing, a timing analysis technique that usually performs well in practice, even though the worst case performance is much worse than either the unit cube or the discrete time approaches. Dill [23] Lewis [41], and Berthomieu and Diaz [8] originated geometric state space exploration, and it has become an active area of research [2, 31, 29] Then, we describe our proposed technique, partial order timing, which improves upon the geometric methods by making use of concurrency and causality information. ....

H. R. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical report, Harvard University, July 1989.

....the time taken to traverse a path in the automaton, not just the time interval between the successive transitions, can be directly expressed. Our model is based on an earlier model proposed by Dill that employs timers [13] A model similar to Dill s was independently proposed and studied by Lewis [30]. He defines state diagrams, and gives a way of translating a circuit description to a state diagram. A state diagram is a finite state machine where every edge is annotated with a matrix of intervals constraining various delays. Lewis also develops an algorithm for checking consistency of the ....

H. Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical Report TR-15-89, Harvard University, 1989.

.... issues severely limited the usefulness of these studies [14] Previous studies in modeling real time systems have focussed on adding the notion of time to the formal modeling techniques of traditional systems, namely logic based [26, 10, 1, 16] Petri net based [27, 24, 11, 17] state based [12, 32, 18, 2, 5], and process algebrabased [28, 13, 3] In all of these studies very little emphasis, if any, was put on the physical nature of the modeled systems. Issues of spontaneity, causality, spacial locality, and reactivity are often disregarded, thus making real time computing research physically ....

Harry Lewis. Finite-state analysis of asynchronous circuits with bounded temporal uncertainty. Technical Report TR15 -89, Department of computer science, Harvard University, Cambridge, MA, June 1989.

....requires energy and thus time. Imposing a positive switching time means that channels have finite capacities and thus cannot carry infinitely many events at the same time. Formally speaking, the switching time is necessary for conducting a finite state analysis on the system s possible behaviors [Lewis:89], Lewis:90] We define the switching time switch A ( of a IOTA A to be a function that maps the set of channels of the IOTA, to the set of positive rationals or positive integers D . For instance, if c i is a channel of A, then switch A (c i ) 2 D denotes the minimum switching time for ....

Harry Lewis, "Finite-state analysis of asynchronous circuits with bounded temporal uncertainty ", Technical report, TR-15-89, Department of computer science, Harvard University, June 1989 (revised July 1989).

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H.R. Lewis, Finite-state Analysis of Asynchronous Circuits with Bounded Temporal Uncertainty, TR15-89, Harvard University, 1989.

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