N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Norwell, MA: Kluwer, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....values. In VLSI implementations of the least mean square (LMS) adaptive filter, for example, this dependence makes the pipelining of the system a challenge. Approximate versions of the adaptive filter that introduce delay within the coefficient updates, such as the delayed LMS algorithm [1, 2], are often employed. In feedforward adaptive control systems, the filtered X LMS algorithm employs a distributed form of delay to approximate a gradient descent procedure on a mean squared error surface [3, 4] Although useful, these modified algorithms usually perform worse than their original ....

N.R. Shanbhag and K.K. Parhi, Pipelined Adaptive Digital Filters (Boston, MA: Kluwer, 1994).

....to operate at such high speed due to the existence of the feedback loops. In order to increase the speed of the algorithms, lookahead techniques [17] can be applied. The so called STAR rotation developed in [18] with application to QRD LSL in [19] and relaxed lookahead technique developed in [20] allows fine grain pipelining with little hardware overhead. However, this is achieved at the cost of degradation of filtering performance due to the approximations in the algorithm. All algorithms in [18 20] are based on multiply add arithmetic. Recently, matrix lookahead technique was developed ....

....in [18] with application to QRD LSL in [19] and relaxed lookahead technique developed in [20] allows fine grain pipelining with little hardware overhead. However, this is achieved at the cost of degradation of filtering performance due to the approximations in the algorithm. All algorithms in [18 20] are based on multiply add arithmetic. Recently, matrix lookahead technique was developed in [21] to achieve fine grain pipelined in QRD RLS adaptive filtering. It is an exact transformation and based on Cordic arithmetic. Furthermore, the transformation does not change the algorithm ....

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N.R. Shanbhag and K.K. Parhi, Pipelined Adaptive Digital Filters, Kluwer Academic Publishers, 1994.

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N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Norwell, MA: Kluwer, 1994.

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N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Norwell, MA: Kluwer, 1994.

....However, they have found applications in low power design as well [9] Algorithm transformation techniques modify the algorithm structure and or performance in order to introduce VLSI friendly features. These techniques include reftming [10] look ahead pipelining [11, 12] relaxed look ahead [13], strength reduction [9, 14] block processing [11, 16] algebraic transformations [17] folding [18, 19] and unfolding [20, 21] which have been employed to design low power and high throughput DSP and communications systems. Another important trade off that is necessary to make is the placement ....

....between power and speed as the supply voltage V is scaled down. In recent years, Vd scaling [24] to reduce power as shown in 6 D 2D Figure 5: Retiming. 8) accompanied by throughput enhancing algorithm transformations (to compensate for loss in speed as indicated by (9) such as pipelining [8, 12, 13] and parallel processing [8, 11] have been proposed as an effective low power technique for DSP applications. 3 Algorithm Transformation Techniques In this section, we will describe static algorithm transformation techniques that modify the properties of a given algorithm so as to enable a VLSI ....

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N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters, Kluwer Academic Pub- lishers, 1994.

....signal to noise ratios ( NR) and or bit error rates (BER) The present trend is to trade off a small amount of performance via algorithm transformation techniques [31] for a much superior VLSI architecture. Algorithm transformation techniques [6,31] such as look ahead [32] relaxed look ahead [37], block processing [33] associa tivity [36] unfolding [15,34] folding [35] retiming [21] have all been employed to design high speed algorithms and architectures. Low power operation was then achieved by trading off excess speed with power. Of particular interest is a class of ....

....path computation time. In fact, application of strength reduction increases the critical path computation time. This results in a throughput limitation, which is undesirable in a high sample rate en vironment. We address this problem via the application of relaxed look ahead transformation [37], which seeks to develop fine grain pipelined architectures by approximating the architectures obtained via the look ahead technique. The relaxed look ahead technique results in a negligible performance loss, while providing a hardware efficient pipelined adaptive filter architecture. This ....

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N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994.

....will be necessary to realize complex VLSI systems for signal processing and communications. One way to integrate algorithmic concerns (such as SNR) and implementation issues such as area, power dissipation and throughput is to employ algorithm transformation techniques [27] such as pipelining [25,28,31], parallel processing [28] unfolding [16] folding [29] retiming [22] etc. Employed traditionally for high speed applications, pipelined algorithms have found use in low power applications as well. Furthermore, by combining pipelining with folding, it is possible to trade off area with speed. ....

....the overall complexity. Therefore, it is desirable to have inherently pipelined adaptive filters, which not only enable us to achieve the required signal to noise ratio (SNt) but also allow us to optimize area, power and speed. Pipelined adaptive digital filters have been proposed recently [31], which are hardware efficient and have similar performance as the unpipelined (or serial) filters. These filters have been developed via the tech nique of relaxed look ahead. This technique is an approximation to the look ahead transformation [28] which had been proposed for fixed coefficient ....

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N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994. 19

....the basic rates of 0.9216 Mcps and 3.6864 Mcps described in CDMA 2000 specifications [1] but not for high bandwidth mode which requires a chip rate of 14.7456 Mcps. The throughput of the chip serial architecture can be improved further via high throughput techniques such as relaxed look ahead [10] pipelining and parallel processing. Note that the critical path in Fig. 3(a) is activated only when the last chip of each symbol is processed. At all other times, the sampling rate is (b) Figure 3: Reconfigurable architectures: a) chip serial and (b) architectures. chip parallel limited by ....

....logic. As the detector processes N chips at a time, the filter can take up to Tsymb to update the W block coefficients. That is, 1T. chip parallel Wchip, 12) assuming that a spreading sequence of length N is used. This architecture can also be pipelined via the relaxed look ahead technique [10] to obtain further speed ups. In summary, the chip serial architecture has very low hardware complexity and is ideal when area is a major concern as in an FPGA implementation. The chip parallel architecture trades area for higher throughput. 3 Reconfigurable MUD based CDMA Archi tectures In ....

N.R. Shanbhag and K.K. Parhi, Pipelined Adaptive Digital Filters, Kluwer Academic Publishers, 1994.

....are equivalent if the Area x Power product is considered. This is due to the fact that a M level parallel architecture requires M times the area of a serial architecture. On the other hand, the area requirements of a pipelined architecture is of the same order as that of a serial architecture [29,31]. In Fig. 12, we have plotted the lower bounds on Pz) for the parallel and pipelined architectures nor malized with respect to that of the serial architecture for values of R W = 10 and R W = 8. As mentioned 22 before, the lower bounds for the parallel architecture are always smaller than that ....

N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994.

....is loaded into the coefficient registers upon chip reset. The feedback filter is also folded by a factor of four to conserve area. This is a complex data, complex coefficient filter so that four real multiplications are required per tap in order to compute the complex output. Strength reduction [8] is used to reduce the number of multiplications required, resulting in an architecture with three real filters rather than four. This provides both area and energy savings. Finally, as an additional power saving strategy, burstmode coefficient updating is employed. It is assumed that ffe0 ffe1 ....

N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Boston, MA: Kluwer Academic Publishers, 1994.

....Fig. 13. Two more signals for 6 D rate. The numbers listed here are not the actual implementation numbers, as the folding algorithm transformation can be used to reduce the final number of hardware elements [22] Simulation results for the receiver equalizer with sum and delay relaxations [23] alongwith folding transformation showed minimal performance degradation. For example, the T1 rate applications (around 1.5 Mbps) can be implemented by inserting only one delay element in the critical path shown in Fig. 5, leading to a valid folding set. This delay relaxation will alter the ....

N. R. Shanbhag and K. K. Parhi, "Pipelined adaptive digital filters," Kluwer, 1994.

.... [2] 4] 5] and have been successfully applied to two dimensional recursive filtering [6] dynamic programming [7] 9] algorithms with quantizer loops [10] finite state machines [8] and Huffman decoders [11] Relaxed look ahead techniques for pipelining of adaptive filters have been proposed [12], and have been successfully applied to LMS adaptive filters [13] stochastic gradient lattice filter [14] the adaptive differential vector quantizer J. Ma and K.K. Parhi are with the Department of Electrical and Computer Engineering at the University of Minnesota, Minneapolis, MN 55455. E.F. ....

N.R. Shanbhag and K.K. Parhi, Pipelined Adaptive Digital Filters, Kluwer Academic Publishers, 1994.

....such as in beamforming, very high sample rates are required, and the QRD RLS algorithm may not be able to operate at such high sample rates. To increase the speed of the QRD RLS, lookahead techniques [6] can be applied. The so called STAR rotation [7] and relaxed lookahead transformation [8] have been developed to allow fine grain pipelining with little hardware overhead. However, this is achieved at the cost of degradation of filtering performance due to the approximations in the algorithms. Both algorithms are based on multiply add arithmetic. If one insists on not using ....

N.R. Shanbhag and K.K. Parhi, Pipelined Adaptive Digital Filters, Kluwer Academic Publishers, 1994.

....can have a large impact on the final power dissipation characteristics of the fabricated VLSI solution. In this paper, we will investigate algorithms and architectures for lowpower and high speed adaptive filters. Algorithm transformation techniques [3] such as lookahead [6] relaxed look ahead [8], block processing, associativity [7] have been employed to design high speed algorithms and architectures. Low power operation is then achieved by trading off excess speed with power. Of particular interest is a class of transformations known as algebraic transformations [7] Strength reduction ....

....power reduction as compared to an architectural level application. The application of strength reduction increases the critical path computation time. This results in a throughput limitation, which is undesirable in high bit rate applications. We address this problem with relaxed look ahead [8] transformation. This transformation results in a fine grain pipelined architecture, which is an approximation of the architecture obtained by lookahead technique. The relaxed look ahead technique maintains the functionality of the algorithm rather than the input output behaviour. Furthermore, it ....

[Article contains additional citation context not shown here]

N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994.

....signalto noise ratios (SNR) and or bit error rates (BER) The present trend is to trade off a small amount of performance via algorithm transformation techniques [31] for a much superior VLSI architecture. Algorithm transformation techniques [6,31] such as look ahead [32] relaxed look ahead [37], block processing [33] associativity [36] unfolding [15,34] folding [35] retiming [21] have all been employed to design high speed algorithms and architectures. Low power operation was then achieved by trading off excess speed with power. Of particular interest is a class of transformations ....

....critical path computation time. In fact, application of strength reduction increases the critical path computation time. This results in a throughput limitation, which is undesirable in a high sample rate environment. We address this problem via the application of relaxed look ahead transformation [37], which seeks to develop fine grain pipelined architectures by approximating the architectures obtained via the lookahead technique. The relaxed look ahead technique results in a negligible performance loss, while providing a hardware efficient pipelined adaptive filter architecture. This ....

[Article contains additional citation context not shown here]

N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994.

....equivalent if the Area Theta Power product is considered. This is due to the fact that a M level parallel architecture requires M times the area of a serial architecture. On the other hand, the area requirements of a pipelined architecture is of the same order as that of a serial architecture [29,31]. In Fig. 12, we have plotted the lower bounds on PD for the parallel and pipelined architectures normalized with respect to that of the serial architecture for values of R=W = 10 and R=W = 8. As mentioned before, the lower bounds for the parallel architecture are always smaller than that of the ....

N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994.

....the critical path of the SR architecture. As explained in [3] both the SR as well as CC architectures are bounded by a maximum possible clock rate due the computations in this critical path. This throughput limitation is eliminated via the application of the relaxed look ahead transformation [7] to the SR architecture (see (2.5 2.6) The relaxed look ahead transformation is an approximation of the look ahead transformation [6] and it results in hardware efficient pipelined adaptive filter architectures. Application of relaxed look ahead to the SR architecture in (2.5 2.6) results in ....

N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994.

....reliability and reduced packaging costs. Power reduction techniques at various levels of design abstraction have been proposed [1] 11] including at the circuit level [21] and via signal encoding [22] At the algorithmic level [13] techniques such as pipelining [2] 24] relaxed look ahead [3], strength reduction [4] block processing [5] and reduced complexity algorithms [23] have been proposed to develop low power algorithms and architectures. These techniques are currently being applied to develop low power and high speed transceivers for applications such as asymmetric digital ....

N. R. Shanbhag and K. K. Parhi, Pipelined Adaptive Digital Filters. Kluwer Academic Publishers, 1994.

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