E. Rotenberg, Q. Jacobson, et al. A study of control independence in superscalar processors. In International Symposium on High-Performance Computer Architecture (HPCA), 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....continue to do so in the future. We propose a novel microarchitecture, called Skipper, to handle difficult branches. Skipper avoids predicting difficult branches by skipping over the computation conditioned by such a branch, and exploits the fundamental property of control flow independence [17]. The computations in a branch s taken and not taken paths are conditioned by the branch and are control flow dependent on the branch because whether each of the computations gets executed or not depends on whether the branch is taken. In contrast, the computation immediately following the ....

....paths reconverge is controlflow independent of the branch because the post reconvergent computation gets executed irrespective whether the branch is taken or not. A previous study shows potential speedups of about 30 in a wide issue superscalar by exploiting control flow independence [17]. Previous approaches to handling difficult branches are: 1) to execute both the taken and not taken paths conditioned by a difficult branch [12,24,11] or (2) upon a misprediction, selectively recover control flow independent instructions by not squashing the data independent instructions, ....

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E. Rotenberg, Q. Jacobson, and J. Smith. A study of control independence in superscalar processors. In 5th international symposium on High Performance Computer Architecture, 1999.

....Electrical and Computer Engr. North Carolina State University University of Wisconsin Madison Control independence is an effective technique for mitigating the effects of branch mispredictions. A recent study shows potential performance improvements of 30 in wide issue superscalar processors [3]. However, practical mechanisms for the three outlined requirements need to be explored. In [3] control dependence information is ideally conveyed from the compiler to hardware for identifying reconvergent points, yet simple hardware only detection of re convergent points is desirable. And the ....

....Control independence is an effective technique for mitigating the effects of branch mispredictions. A recent study shows potential performance improvements of 30 in wide issue superscalar processors [3] However, practical mechanisms for the three outlined requirements need to be explored. In [3], control dependence information is ideally conveyed from the compiler to hardware for identifying reconvergent points, yet simple hardware only detection of re convergent points is desirable. And the reorder buffer of superscalar processors is managed as a fifo with insertion and removal of ....

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E. Rotenberg, Q. Jacobson, and J. Smith. A study of control independence in superscalar processors. 5th Intl. Symp. on High Perf. Comp. Arch., Jan 1999.

....instruction and the first instruction which requires its result to overlap the handler with the faulting thread. Our proposed mechanism exploits the control independence present in exception handler execution. Micro architectures with general mechanisms for exploiting control independence [13] should be able to likewise exploit this aspect of exception handlers. 8 Conclusion This paper presents a new exception architecture which uses idle threads in a multithreaded processor to execute exception handlers. The exception handler is executed in a separate thread, but instructions are ....

E. Rotenberg, Q. Jacobsen, J. Smith. A Study of Control Independence in Superscalar Processors. In Proc. of the 5th International Symposium on High-Performance Computer Architecture, January 1999.

....CP Bit Mask and the WP Bit Mask. 1. The Alpha ISA on which our simulator is based specifies 32 integer registers and 32 floating point registers. The lower 32 bits represent the 32 integer registers and the upper 32 bits represent the 32 floating point registers. 2. Unlike the scheme described in [24], this scheme does not require the processor to support selective reissue. 6 After a mispredicted branch is detected and before the first control independent instruction is found, the correct path store instructions write their effective addresses into the CP Store Buffer. When the first ....

....information (the SP CD model in their paper) can potentially achieve on the average twice as much parallelism as one which does not. Being a limit study, they assume unlimited resources like an infinite instruction issue window and an infinite number of functional units. Rotenberg et al. s [24] recent study on control independence in superscalar processors explored the performance potential of control independence under limitation constraints (i.e. limited instruction widow sizes and limited fetch and issue bandwidth) and sought to understand the factors that contribute to or limit the ....

Eric Rotenberg, Quinn Jacobson, and Jim Smith, "A Study of Control Independence in Superscalar Processors," to appear in Proc. of 5th International Conference on High Performance Computer Architectures, January 1999.

....fetched executed regardless of the outcome of the branch; this typically occurs when the two paths following a branch re converge before the control independent traces. Control independent traces do not have to be squashed and restarted if the branch is mispredicted. A recent study we have done [ROT99] explores the potential and limitations of control independence in the context of superscalar processors. Control independence can potentially reduce the performance gap between real and oracle branch prediction by half. In a detailed implementation, performance improvements on the order of 30 ....

E. Rotenberg, Q.A. Jacobson, J.E. Smith, "A Study of Control Independence in Superscalar Processors," to appear Fifth Intl. Symp. on High Perf. Comp. Arch., January 1999.

....spite of mispredicted branches by exploiting control independence. A trace is control independent of a prior branch if the trace is executed regardless of the outcome of the branch. Control independent traces do not have to be squashed and restarted if the branch is mispredicted. A recent study [2] explores the potential and limitations of control independence in the context of superscalar processors. It predicts that control independence can reduce the performance gap between real and oracle branch prediction by half. In a detailed simulation, overall performance improvements on the order ....

E. Rotenberg, Q. A. Jacobson, J. E. Smith, "A Study of Control Independence in Superscalar Processors, " Fifth Intl. Symp. on High Perf. Comp. Arch., pp. 115-124, January 1999.

....insertion removal. Further, the abstract nWR FD model suggests combining the expandable window model of multiscalar processors with the aggressive data dependence resolution and recovery model of trace processors. A much more comprehensive treatment of control independence can be found in [28], an extension of this paper. Acknowledgments This work was supported in part by NSF Grant MIP 9505853 and by the U.S. Army Intelligence Center and Fort Huachuca under Contract DABT63 95 C 0127 and ARPA order no. D346. The views and conclusions contained herein are those of the authors and ....

E. Rotenberg, Q. Jacobson, and J. Smith. A study of control independence in superscalar processors. Technical Report 1389, Univ. of Wisc., CS Dept., Nov 1998.

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Rotenberg, E., Jacobson, Q., & Smith, J. (1999a). A study of control independence in superscalar processors. In Proceedings of the 5th International Symposium on High Performance Computer Architecture.

....the first a novel application of value prediction [51,87,27] to break inter trace data dependences and the second a variant of the address resolution buffer [24] for speculative memory disambiguation. Section 1.2. 2 describes a sophisticated control flow management technique, control independence [46,20,83], for maintaining accurate instruction windows despite trace mispredictions. 12 1.2.1 Data speculation techniques 1.2.1.1 Live in prediction When a trace is renamed and dispatched to a PE, its live in values are predicted (Figure 1 1) Predicting live in values as opposed to predicting all ....

....on the branch outcome, however. These instructions are control dependent on the branch. Other instructions deeper in the window may be control independent of the mispredicted branch: they will be fetched regardless of the branch outcome, and do not necessarily have to be squashed and re executed [46,20,83]. Control independence typically occurs when the two paths following a branch re converge before the control independent instruction, as depicted in Figure 1 5. Upon detecting the misprediction, the incorrect control dependent instructions are squashed and replaced with the correct control ....

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E. Rotenberg, Q. Jacobson, and J. Smith. A Study of Control Independence in Superscalar Processors. 5th International Symposium on High-Performance Computer Architecture, January 1999.

....can fetch along a single flow of control at any given time. The instruction window is a contiguous set of dynamic instructions. Control independence is implemented by allowing the program counter to skip back and forth in the dynamic instruction stream. Superscalar processors fall into this class [82]. 38 Each class of machines has advantages. With implementations having multiple flows of control, there is a natural hierarchical structure: each flow of control fetches and operates on its own task or thread. Control decisions are separated into inter task and intra task levels. Intra task ....

....Upon detecting a mispredicted branch, entire threads are re fetched from buffers and analyzed to isolate data dependent, control independent instructions, and these instructions are selectively re executed. 2.4. 3 Control independence in superscalar processors Rotenberg, Jacobson, and Smith [82,83] examine the potential of control independence in the context of wide issue superscalar processors. An aggressive implementation achieves improvements on the order of 30 . The proposed mechanisms are complex due to the non hierarchical superscalar organization, and there is a reliance on the ....

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E. Rotenberg, Q. Jacobson, and J. Smith. A Study of Control Independence in Superscalar Processors. Technical Report CS-TR-98-1389, Computer Sciences Department, University of Wisconsin - Madison, December 1998.

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E. Rotenberg, Q. Jacobson, et al. A study of control independence in superscalar processors. In International Symposium on High-Performance Computer Architecture (HPCA), 1999.

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E. Rotenberg, Q. Jacobson, and J. Smith. A study of control independence in superscalar processors. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Jan. 1999.

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E. Rotenberg, Q. Jacobson, and J. E. Smith. A study of control independence in superscalar processors. In Proceedings of the Fifth IEEE International Symposium on High Performance Computer Architecture, 1999.

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E. Rotenberg, Q. Jacobson, and J. E. Smith. A study of control independence in superscalar processors. In Proceedings of the Fifth IEEE International Symposium on High Performance Computer Architecture, pages 115--124, 1999.

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E. Rotenberg, Q. Jacobson, and J. E. Smith. A study of control independence in superscalar processors. In Proceedings of The Fifth International Symposium on High-Performance Computer Architecture (HPCA'99), pages 115--124, January 1999.

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E. Rotenberg, Q. Jacobson, and J. E. Smith. A study of control independence in superscalar processors. In Proceedings of The Fifth International Symposium on High-Performance Computer Architecture (HPCA'99), pages 115--124, January 1999.

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