"Eldredge, J., Hutchings, B., "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs", in Journal of VLSI Signal Processing, Volume 12, 1996. Pages 67-86  Home/Search   Document Details and Download   Summary   Related Articles   Check

....This can be expensive to implement on FPGAs as the number of nodes and connectivity within the network grows. Several techniques have been used to reduce this problem: implementation of partially connected neural networks [10] and time multiplexing of network nodes using partial reconfiguration [11]. FPGA implementations can provide significant speed up compared to software implementations, and have the advantage of flexibility, which is of benefit to many applications. However, for other applications FPGAs cannot provide sufficient densities of neurons and ASIC implementations, often ....

Eldredge, J.G. and B.L.Hutchings, Run-Time Reconfiguration: a method for enhancing the functional density of SRAM-based FPGAs. Journal of VLSI Signal Processing, 1996. 12(1): p. 67-86.

....low. RTR can be further divided into global and local RTR. In global RTR, the complete FPGA is reconfigured. To achieve an acceptable FPGA utilization, the application must be partitioned into segments with roughly equally sized hardware requirements. An example for a global RTR system is RRANN [15]. RRANN implements the backpropagation training algorithm for neural networks in three segments. A further application class for RTR is pattern matching, where huge amounts of data have to be compared with di#erent templates. For each template dedicated hardware is designed, leading to high ....

J. G. Eldredge and B. L. Hutchings. Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-based FPGAs. Journal of VLSI Signal Processing, 12(1):67--86, January 1996.

....1. INTRODUCTION Run time reconfigurable (RTR) custom computing machines (CCMs) are systems that take advantage of the programmable nature of the FPGA by utilizing multiple configurations. RTR CCMs can solve problems that require more resources than are available on all the FPGAs in the system [EldH96]. They accomplish this by partitioning the problem into stages that fit in the available FPGA logic. The RTR CCM calculates a portion of the problem and then stores the intermediate results. Then the CCM reconfigures the FPGAs for another part of the computation and continues where the last ....

J. G. Eldredge, B. L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs," Journal of VLSI Signal Processing, vol. 12, pp. 67-86, 1996.

....Also, as a technology, it has the potential to reduce overall system life cycle and maintenance costs. Although much attention has been given to the development of new, innovative architectures for configurable computing [3] 30] and investigating applications of configurable computing [13][27] little effort has been invested in developing assessment techniques for configurable computing systems. These techniques can be used to determine which systems will best satisfy a user s overall requirements. Benchmarking is commonly used for evaluating the hardware and software of ....

Eldredge, J. G., and Hutchings, B. L., Run-time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-based FPGAs. Journal of VLSI Signal Processing 12, 1996. 67-86.

....reconfigurable systems comes at the expense of the reconfiguration time. The amount of time required to set the function to be implemented on the reconfigurable logic is the configuration time, which can become a serious bottleneck especially in systems where run time reconfiguration is performed [4, 5]. We propose a new architecture for a system that uses reconfigurable logic, which we refer to as Strategically Programmable System (SPS) The basic building blocks of our architecture are parameterized functional blocks that are pre placed within a fully reconfigurable fabric. They are called ....

J. G. Eldredge and B. L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs", in Journal of VLSI Signal Processing, Volume 12, 1996.

....and will re do the whole thing after every iteration. They are not suitable for supporting large designs with possible multiple design iterations. Fast incremental compilation techniques are e specially important for supporting such applications as well as runtime configuration applications [9]. This work on incremental technology mapping is a part of an overall effort at UCLA in d eveloping a highly efficient incremental compilation system for FPGAs. The incremental technology mapping system should consider the following three important objectives: 1. Preservability . The ....

J. G. Eldredge and B. L. Hutchings. Run-time reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs, Journal of VLSI Signal Processing, v.12: pp. 7--86, 1996

....Programmable Gate Array (FPGA) Reconfiguration, Resource Management, Scheduling I. Introduction Adaptive Computing Systems (ACS) have been shown to outperform general purpose systems for some applications because of their abilities in adapting hardware resources to the application requirements[1], 8] 9] 13] 16] The technology has been demonstrated for a few special purpose applications which have been tediously handcoded. These systems also have tremendous promise for accelerating more conventional applications such as domain specific visual development environments (Khoros, ....

....time for an individual application. Since all of the required FPGA resources need not be loaded at once, a larger portion of the application computation can be mapped to FPGAs. ffl Compared to other dynamic reconfiguration schemes that statically determine how to reuse the FPGA resources [1], 2] the system allocates FPGA resources at run time via a RM that relieves application developers from the management of FPGA resources. Due to use of the RM and its speculative loading policy, multiple applications may share the FPGA resources effectively, very much analogous to a virtual ....

J.G. Eldrege and B.L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-based FPGAs," in Journal of VLSI Signal Processing, Volume 12, pp. 67-86, 1996.

....of field programmable gate array (FPGA) technology has enabled the implementation of an entire DSP algorithm on a circuit board with multiple FPGA chips. Impressive performance improvements have been reported for applications on various reconfigurable computing systems that contain FPGA boards [9], 14] 22] 37] 39] One current difficulty in exploring the technology is associated with the tedious process of mapping algorithms to an FPGA board. Given an application algorithm, designers usually first intuitively produce a circuit design and then try to partition (either single chip or ....

J.G. Eldrege and B.L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-based FPGAs," in Journal of VLSI Signal Processing, Volume 12, pp. 67-86, 1996.

....that use co processor boards based on field programmable gate array (FPGA) chips may adapt their hardware resources to the application requirements. The technology has been demonstrated for the acceleration of various applications, such as automatic target recognition (ATR) 1] neural networks[2, 3, 4], Adobe Photoshop [5] Solar Polarimetry[6] and machine vision[7] This paper describes the acceleration of an infrared (IR) ATR application with a multiple FPGA board and the development of an FPGA resource manager software system. The software system supports dynamic reconfiguration so that the ....

....RM can accommodate more applications, typically those that require more FPGA resources than what is available and their usage of FPGA resources can be satisfied once spread out over time. Compared to other dynamic reconfiguration schemes that statically determine how to reuse the FPGA resources [3, 8], the RM of our system allocates FPGA resources at run time and relieves application developers from the management of FPGA resources. The RAGE project [9] is similar to our own, but paper.tex; 23 07 1999; 15:43; p.2 3 emphasizes partial reconfiguration. It does not support pre loading of ....

J.G. Eldrege and B.L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-based FPGAs," in Journal of VLSI Signal Processing, Volume 12, pp. 67-86, 1996.

....the cache itself is rather primitive. The Least Recently Used (LRU) algorithm is used to determine which segment of the cache to remove for a new entry and an onboard controller implements this simple algorithm. Each cachable instruction must be explicitly loaded into the FPGA before it is needed[8]. A high level of hardware design knowledge is needed to produce an efficient program implementation on this system. Each new application will most likely require new instructions to be manually designed. No automatic synthesis is performed on extracted segments of code. 2 System Hardware ....

J. G. Eldredge and B. L. Hutchings, "Run Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM Based FPGAs", VLSI Signal Processing, V. 12, pp. 67--86, 1996.

....constructed that attains near ASIC performance. 2. Cost Effectiveness. Configurable computing can be used to reduce system costs through two approaches: hardware reuse and low NRE. A number of research efforts have demonstrated time shared methods for simulating a large circuit on a smaller FPGA [SJ95,EH94,EH96]. For example, the UCLA image compression work swapped four different circuit configurations onto a National Clay FPGA. Since the clock speed of the FPGA was more than 4X greater than the required circuit speed, the system achieved comparable performance at one quarter of the hardware costs. The ....

....execution. With RTR, configurations are cooperative; configurations interact with one configuration typically producing a result that is consumed by some succeeding configuration. There have been several demonstrations of RTR, for example DISC, the Mojave project at UCLA [V96] and RRANN. RRANN [EH96, EH94] was perhaps the earliest demonstration of an RTR system. It divided the popular backpropagation algorithm used to train neural networks into 3 temporally exclusive circuits (configurations) each implementing part of the overall algorithm. For neural networks of moderate size (150 neurons per ....

J. G. Eldredge and B. L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs", Journal of VLSI Signal Processing", Vol. 12, 1996.

....count is determined by the number of non output neurons in the network (N) and the number of layers (l) as follows (adapted from Equation 7 of [23] 1 ) cycle count = l Gamma1 X x=1 Nodes[x] Theta 148 (l Gamma 1) Theta 13 282: 5. 4) 1 A more accurate equation described in [91] considers the quantization errors associated with larger networks. The added execution time required to address the quantization error is negligible and does not effect the results of this analysis. 49 Multiplying the cycle count by the clock rate and applying the assumptions stated above (l = ....

J. G. Eldredge and B. L. Hutchings. Run-time reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs. Journal of VLSI Signal Processing, 12:67--86, 1996.

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"Eldredge, J., Hutchings, B., "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs", in Journal of VLSI Signal Processing, Volume 12, 1996. Pages 67-86

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J. Eldredge and B. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs," in Journal of VLSI Signal Processing, Volume 12, 1996.

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J.G. Eldredge and B.L. Hutchings, "Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs," Journal of VLSI Signal Processing, Volume 12, pp. 67-86, 1996.

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J. G. Eldredge and B. L. Hutchings, "Run-time reconfiguration: a method for enhancing the functional density of SRAM based FPGAs," Journal of VLSI in signal processing, Volume 12, 1996. Pages 67-86

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