W. Richardson and E. Brunvand. Fred: An Architecture for a Self-Timed Decoupled Computer. In Proceedings of the Second International Symposium in Asynchronous Circuits and Systems, pages 60--68. IEEE Computer Society Press, June 1996. 24  Home/Search   Document Details and Download   Summary   Related Articles   Check

....out of order instruction completion. It handles exceptions and interrupts. Several features of the Fred architecture are directly related to its self timed design, such as the decoupled branch mechanism and exception model. Early versions of the Fred architecture have been discussed elsewhere [33,34]. Detailed descriptions of the most recent implementation are contained in the following chapters. 1 Fred is not an acronym, and it does not mean anything. It is just a name, like Pentium or Alpha. 8 9 CHAPTER 3 MICROPIPELINES Although self timed circuits can be designed in a variety of ....

W. F. Richardson and E. Brunvand, "Fred: An architecture for a self-timed decoupled computer," Technical Report UUCS--95--008, University of Utah, May 1995. ftp:// ftp.cs.utah.edu/techreports/1995/UUCS-95-008.ps.Z.

.... instance, QDI for critical pipelined datapaths) One can see that some architectures are derived from a synchronous one (Amulet, MiniMIPS, TinyRISC, Titac 2, C51) while others have been designed with their proprietary instruction sets (ASPRO, 16 bit NSR and 32 bit FRED, from the University of Utah [6, 7]) The following Table gives the performances of these microprocessors. There are other projects leaded by Intel and Sun labs [9] Year Microprocessor MIPS Vdd Power MIPS Watt 199x Amulet 1 [2] 12 5.0 152 mW 77 ....

....for a 0.6 m CMOS technology even if the stages are very simple. The ASPRO 16 bit RISC [13] is a similar design with pipeline stages with delays of about 1 ns (1 GHz) The throughput is about 200 MIPS, meaning that on average only one stage over 5 is occupied. With short asynchronous pipelines [6, 7], it is simpler to block the flow of instructions early in the pipeline until the condition is evaluated and one knows that the branch will be taken or not. Of course one could execute instructions and kill them later with a minor penalty, but this would require more complex control circuits to ....

W. F. Richardson, E. L. Brunvand, FRED : An Architecture for a Self-Timed Decoupled Computer », Computer Science Department, University of Utah, 1997.

....Fred architecture are directly related to its 1. Fred is not an acronym, and it doesn t mean anything. It s just a name, like Pentium or Alpha. self timed design, such as the decoupled branch mechanism and exception model. Early versions of the Fred architecture have been discussed elsewhere [9,10,11]. A prototype of Fred has been implemented as a detailed VHDL model to investigate the performance 2 and behavior of the Fred architecture under varying conditions. Figure 1 shows the overall organization. Each box in the figure is a self timed process communicating via dedicated data paths ....

William F. Richardson and Erik Brunvand. Fred: An architecture for a self-timed decoupled computer. In Proceedings of the Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, AizuWakamatsu, Japan, March 1996.

....Fred architecture are directly related to its 1. Fred is not an acronym, and it doesn t mean anything. It s just a name, like Pentium or Alpha. self timed design, such as the decoupled branch mechanism and exception model. Early versions of the Fred architecture have been discussed elsewhere [9,10,11]. A prototype of Fred has been implemented as a detailed VHDL model to investigate the performance 2 and behavior of the Fred architecture under varying conditions. Figure 1 shows the overall organization. Each box in the figure is a self timed process communicating via dedicated data paths ....

William F. Richardson and Erik Brunvand. Fred: An architecture for a self-timed decoupled computer. Technical Report UUCS--95--008, University of Utah, May 1995. ftp://ftp.cs.utah.edu/techreports/1995/ UUCS-95-008.ps.Z.

....(Non Synchronous RISC) architecture developed at the University of Utah [1,5] The NSR is a simple 16 bit machine designed to explore the potential of self timed organization for computer design, but includes little support for anything but the basic microprocessor features. The Fred architecture [6] borrows many ideas from the NSR. However, Fred includes 32 bit data paths and memory addressing, provides a larger register file, and extends the instruction set in a variety of ways that make the architecture more realistic and more comparable to commercial microprocessors. More importantly, ....

....paths for instructions and data. Fred contains 32 32 bit general purpose registers, two of which have special usage. Register r0 is hardwired to zero, and register r1 is used to access the R1 Queue. This data pipeline is used to queue up data for later use by another part of the instruction stream [6,12]. Loads from memory, for example, might be queued in the R1 Queue by using register r1 as the destination. By using r1 as a source register, a later instruction dequeues the next word from the R1 Queue and uses it as an operand. It may be possible to subsume some of the memory latency by queuing ....

William F. Richardson and Erik Brunvand. Fred: An architecture for a self-timed decoupled computer. Technical Report UUCS--95--008, University of Utah, May 1995. ftp://ftp.cs.utah.edu/techreports/1995/UUCS95 -008.ps.Z.

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W. Richardson and E. Brunvand. Fred: An Architecture for a Self-Timed Decoupled Computer. In Proceedings of the Second International Symposium in Asynchronous Circuits and Systems, pages 60--68. IEEE Computer Society Press, June 1996. 24

No context found.

W. F. Richardson, E. Brunvand. Fred: An Architecture for a Self-Timed Decoupled Computer. IEE Proceedings on Computers and Digital Techniques, vol. 143, no. 5, September 1996

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