K. Keeton, R. Arpaci-Dusseau, D. A. Patterson, "IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck", Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, International Symposium on Computer Architecture, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....has a processor that performs computations (usually data compression) on the fly to the data. Systems of the future will export computation to such devices. Similarly, the next generation of memory chips will combine processors and memory on the same chip, this is called processing in memory (PIM) [9, 7]. Such memory components can assist the processor in accomplishing a task. Consequently, memory assisted computations will become typical. Therefore, pushing computation out of the main processor will provide performance benefits as well as programming benefits. Additionally, the MonA file ....

....system pushes computation into the operating system and provides a framework through which collaborative memory architectures exploit these computations. Although several research institutions and corporations are developing PIM architectures, most are still in the latter stages of development [9, 7, 4, 3]. As a result, initial research on collaborative software has focused on providing a general mechanism for logically pushing calculations into memory. In addition to modifying data, the file system provides multiple concurrent paths to raw data. Thus, the method by which data is accessed ....

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Kimberly Keeton, Remzi Arpaci-Dusseau, and David A. Patterson. IRAM and SmartSIMM: Overcoming the I/O bus bottleneck. In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97. June 1997.

....anonymous referees. This work is supported in part by an NSF CAREER award to Fred Chong, by NSF grant CCR 9812415, by grants from Altera, and by grants from the UC Davis Academic Senate. More info at http: arch.cs. ucdavis.edu AP Now at University of California, San Diego memory gap [P 97] KADP97] These improvements, however, are limited to single chip systems with limited memory requirements such as PDAs. We expect that the memory demands of most systems will scale with DRAM density, and multiple memory chips will be required. We introduce Active Pages, a page based architecture for ....

Kimberly Keeton, Remzi Arpaci-Dusseau, and David A. Patterson. IRAM and SmartSIMM: Overcoming the I/O bus bottleneck,. In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, Colorado, June 1997.

....we plan to release the file system source in the near future. Lastly, intelligent devices, those with integrated processing capabili22 ties, will be the standard in the future. Today, processors are being incorporated in disk drives [1, 5] communication devices [15, 21] and even memory [14, 12]. To effectively harness the power of these intelligent devices, an appropriate systems programming model is needed. The model should: ffl share the workload between applications and intelligent devices, ffl support the increased functionality of intelligent devices, and ffl do the above ....

Kimberly Keeton, Remzi Arpaci-Dusseau, and David A. Patterson. IRAM and SmartSIMM: Overcoming the I/O bus bottleneck. In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97. June 1997.

....show that many extensions are viable even with an incredibly slow I O processor. A faster CPU, for example, would allow the use of a virtual machine interpreter (e.g. Java) enabling transparent execution of extensions regardless of the instruction set. Using a vector processor, as suggested in [54] of the IRAM project, would enable data touching intensive applications, such as encryption, compression, video decoding, and data filtering, to be implemented on the network adapter. Based on our experience with the LANai, we believe that more aggressive processor and hardware structures would ....

K. Keeton, R. Apraci-Dusseau and D.A. Patterson. "IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck." In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember. 1997.

....This research was supported by the JPL HTMT project, Arthur J. Schmitt Fellowship, and ND Faculty Research Program. are active. Disk and tape drives perform computations (usually data compression) on the fly to the data. Intelligent memory technology combines processors and RAM on the same chip [13, 12, 6]. In the future, memory assisted computations will be typical. The primary element of collaborative memory is modify on access (MonA) memory, which implicitly operates on (modifies) the memory when it is accessed by a process. An input transform modifies data as it is read and an output ....

....to devices, memory, privileged instructions, and CPU resources. This is similar in principle to SPIN; however, the technique is different. The untrusted module will not execute as fast as in SPIN, but any language can be used. Several intelligent memory systems are currently under development [12, 14, 6, 11]. These systems combine processors and memory on the same chip and present tremendous opportunities for computation. Intelligent memory becomes a viable architecture for transformation programming by combining very high processor to memory bandwidth with short memory access times. The IRAM ....

[Article contains additional citation context not shown here]

Kimberly Keeton, Remzi Arpaci-Dusseau, and David A. Patterson. IRAM and SmartSIMM: Overcoming the I/O bus bottleneck. In Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97. http://iram.cs.berkeley.edu/isca97workshop /, Denver, CO, June 1997.

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K. Keeton, R. Arpaci-Dusseau, and D.A. Patterson, "IRAM and SmartSIMM:Overcoming the I/O Bus Bottleneck," http://iram.cs. berkeley.edu/isca97-workshop/ (current July 23, 1997).

....for network communication and other serial lines connect them to disks could allow this cluster to sort more than 100 GB in a minute. Given that the high volume applications above need inexpensive IRAMs, the cost of 16 32 IRAMs would likely be much less than 10 of the disk infrastructure cost. [7] Greg Papadopolous, Chief Technical Officer of Sun Microsystems Computing Corporation, observed a trend in data mining. 12] While processors are doubling performance every 18 months, customers are doubling data storage every 5 months. Customers would like to mine this data overnight to shape ....

....speed 450 GB s 2000 GB s Floor space 1600 sq. ft. 10 sq. ft. Cost 55,000,000 500,000 Year 1996 2000 Figure 2. Supercomputing clusters. 4. IRAM Architectures and Implementations Putting a conventional cache based, superscalar microprocessor in an IRAM does not lead to exciting performance. [7][14] Hence IRAM needs a new architecture. If an architecture requires programmers to rewrite their programs, then it needs advantages of factors of at least 10 and as much as 50. 15] The reason for this high threshold is that software development is slow, and with conventional microprocessor ....

Keeton, K.; Arpaci-Dusseau, R; and Patterson, D; "IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck," Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, Denver, CO, USA, 1 June 1997. (http://iram.cs.berkeley.edu/isca97-workshop/w2-120-draft.ps)

....case, the off chip memory could be managed as secondary storage with pages swapped between on chip and off chip memory. Alternatively, multiple IRAMs could be interconnected with a high speed network to form a parallel computer. Ways to achieve this have already been proposed in the literature [9] [10] 11] However, historical trends indicate that the end user demand for memory scales at a much lower rate than the available capacity per chip. So, over time a single IRAM will be sufficient for increasingly larger systems, from portable and low end PCs to workstations and servers. Finally, ....

K.Keeton, R.Arpaci-Dusseau, D.A.Patterson, "IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck", Workshop on Mixing Logic and DRAM, ISCA-97, Denver, CO, 1 June 1997.

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K. Keeton, R. Arpaci-Dusseau, D. A. Patterson, "IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck", Workshop on Mixing Logic and DRAM: Chips that Compute and Remember, International Symposium on Computer Architecture, 1997.

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