H. C. Torng and Martin Day.Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(, ,January 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....all been issued, while the unshaded ones have not. To properly resume execution after interrupt handling, the unshaded instructions must be re executed. Some mechanism that can selectively execute these instructions is necessary. The restart mechanism illustrated in Fig. 5 is that suggested by [10]. In this approach, it is assumed that the implementation issues instructions out of an instruction window. On an interrupt, those instructions in the instruction window that have not completed are saved (as is the address of the next instruction to be fetched into the window) Normal instruction ....

H.C. Torng and M. Day. Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(1):122--127, January 1993.

....a faster device longer than tolerable [47, 49] Such an interrupt mechanism requires both, hardware support and a software protocol to be obeyed, and therefore, it is acknowledged to be a particularly hard part of machine design ( 19] p. 214) Even most recent publications on interrupt handling [19, 45, 47, 49, 52, 54, 55] sketch only parts of those mechanisms. Usually, they ignore the interactions of the software protocol and the hardware support, or restrict the solutions to the sequential processing of interrupts. With the notable exception of [25] no attempt is made to prove the correctness of an interrupt ....

H.C. Torng and M. Day. Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(1):122--127, 1993.

....handling by aborting and subsequently restarting operations that are in execution beyond the point of the excepting operation or the point at which the interrupt occurs. Ozer [39] proposes the use of a Current State Buffer which is a variation of the Instruction Window approach by Torng and Day [56] that is tailored for VLIW processors. Corporaal [13] proposes several different collection techniques (run out buffers, look ahead buffers and hidden state buffers, and busflash units) which preserve result data in the event of an interruption. In this section we describe the basic behavior of ....

H. C. Torng and Martin Day. Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(1):122--127, January 1993.

....individual instructions may complete in a different order than which they were issued. FRED: AN ARCHITECTURE FOR A SELF TIMED DECOUPLED COMPUTER 8 4.2. 1 The Instruction Window An Instruction Window (IW) is used to buffer incoming instructions and to track the status of issued instructions [19]. A register scoreboard is used to avoid all data hazards. The IW is a set of internal registers located in the Dispatch unit which tracks the state of all current instructions. Each slot in the IW contains information about each instruction such as its opcode, address, current status, and various ....

....but there is no actual register associated with the R1 Queue. Instead, the Dispatch unit clears the scoreboard bit for register r1 when the producing instruction completes successfully. FRED: AN ARCHITECTURE FOR A SELF TIMED DECOUPLED COMPUTER 11 5 Exceptions Fred uses an Instruction Window [19] in the Dispatch unit to maintain the status of all current instructions. Exceptions are functionally precise. The exception model seen by the programmer is not that of a single point where the exception occurred. Instead, there is a set of instructions which were in progress. The hardware ....

H. C. Torng and Martin Day. Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(1):122--127, January 1993. FRED: AN ARCHITECTURE FOR A SELF-TIMED DECOUPLED COMPUTER 13

....hazards. The scoreboard is set by the Dispatch Unit and is cleared when results arrive at the Register File. Instructions will not be dispatched until all data hazards are resolved. An Instruction Window (IW) is used to buffer incoming instructions and to track the status of issued instructions [42]. The IW is a set of internal registers located in the Dispatch Unit which tracks the state of all current instructions. Each slot in the IW contains information about each instruction such as its opcode, address, current status, and various other parameters. As each instruction is fetched, it is ....

....its single ALU causes all instructions to issue and complete sequentially. Fred s decoupled concurrent architecture requires a more general solution. 5.1.1. The Instruction Window To resolve the uncertainty regarding instruction status, Fred uses an IW, similar to that described by Torng and Day [42], to fetch and dispatch instructions. The IW is a set of internal registers located in the Dispatch Unit, which tracks the state of all current instructions. Each slot in the IW contains information about each instruction, such as its opcode, its address, its current status, and various other ....

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H. C. Torng and M. Day, "Interrupt handling for out-of-order execution processors," IEEE Transactions on Computers, vol. 42, pp. 122--127, January 1993.

.... key concept of modern CPUs [7] Precise interrupts are required by many techniques, like IEEE floating point arithmetic, virtual memory, or fast I O [8] There exist several mechanisms for implementing precise interrupts such as the reorder buffer, the future file[7] and the instruction window [9]. The reorder buffer is most commonly used. In this paper supported by the DFG graduate program Effizienz und Komplexitat von Algorithmen und Rechenanlagen y partially supported by the German Science Foundation DFG we therefore analyze a variant of the Tomasulo scheduler with a reorder ....

H.C. Torng and Martin Day. Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(1):122--127, 1993.

....to be obeyed, but the design of protocols of any kind is one of the most error prone activities in computer science. Thus, it is no wonder that interrupt handling is acknowledged to be a particularly hard part of machine design ( 1] p. 214) and that most publications on interrupt handling [1, 5, 6, 7, 8, 9, 10] sketch only parts of those mechanisms. Usually, they ignore the interactions of the software protocol and the hardware support, or restrict the solutions to the sequential processing of interrupts. However, those simplifications can by no mean be tolerated in modern operating systems [6, 7] The ....

....JISR JISR 0 SR CA3, pfls, misa Figure 6: Pre computing interrupt signal JISRp 6 Conclusions The main contribution of this paper is an independent set of hardware software constraints of a correct mechanism for precise nested processing of interrupt. Based on these constraints, the solutions in [5, 6, 7, 8, 9, 10] for precise interrupt handling are therefore applicable to nested processing as well. ....

H.C. Torng and M. Day. Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(1):122--127, 1993.

....committed. If the prediction was incorrect, then the results of speculatively executed instructions are discarded, and instructions are fetched and executed from the correct path. Several dynamic techniques have been proposed to implement speculative execution coupled with precise state recovery [73, 74, 115, 116, 138, 147, 154]. Hardware schedulers often use simplistic heuristics to choose from the instructions that are ready for execution. This is because any sophistication of the instruction scheduler directly impacts the hardware complexity. A number of dynamic scheduling techniques have been proposed: CDC 6600 s ....

....file; instead they are routed only to the RUU to allow waiting instructions to pick up their data. Results are forwarded to the register file in sequential order, as and when instructions are committed from the RUU. Dispatch Stack: The dispatch stack is a technique proposed by Acosta et al. [4, 154]. The hardware features for carrying out this scheme are: two dependency count fields associated with each register, and a dispatch stack. The dependency count fields of a register are for holding the number of pending uses of the register (the number of anti dependencies) and the number of ....

H. C. Torng and M. Day, "Interrupt Handling for Out-of-Order Execution Processors," Technical Report EE-CEG-90-5, School of Electrical Engineering, Cornell University, June 1990.

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H. C. Torng and Martin Day.Interrupt handling for out-of-order execution processors. IEEE Transactions on Computers, 42(, ,January 1993.

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