K. Fisler. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Computer Science Department, Indiana University, August 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....SRC Contract 97 DP 388. E mail: namla cs.utexas.edu URL: http: www.cs.utexas.edu users namla E mail: emerson cs.utexas.edu URL: http: www.cs. utexas.edu users emerson E mail: kedar research.bell labs.com URL: http: cm.bell labs.com cm cs who kedar 1 satisfy a timing diagram Fisler [13] defines two kinds of semantics: in the invariant semantics, the timing diagram must be satisfied at every state of a computation, while in the basic iterative semantics, the diagram must be satisfied iteratively. We introduce a generalization of the iterative semantics, in which a timing diagram ....

....are given. Many other researchers [1, 22, 19, 4] have formalized timing diagrams and translated them to other formalisms (interval logics, trigger graphs etc) Formal notions of timing diagrams are also proving to be useful in test generation and logic synthesis (cf. 23, 15, 12] Fisler [13, 14] proposes a timing diagram syntax and semantics that allows non regular languages, and finds that these languages occur at all levels of the Chomsky hierarchy. The paper [14] provides a decision procedure that determines whether a regular language is contained in an unambiguous timing diagram ....

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K. Fisler. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Computer Science Department, Indiana University, August 1996.

....a falling edge (falling edge triggered) In the SRTD in Figure 1, signals p and r are falling edge triggered while q is rising edge triggered. Timing diagrams may either be unambiguous, where the events are linearly ordered, or ambiguous, where the events are partially ordered with respect to time [11]. Synchronous timing diagrams are generally unambiguous but the don t care transitions do introduce some degree of ambiguity in SRTD s. 2.1 Syntax In most applications of timing diagrams, the waveform behavior specified by the diagram must hold of a system only after a certain precondition ....

K. Fisler. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Computer Science Department, Indiana University, August 1996.

....such RTD s are called ambiguous. An unambiguous RTD has a total ordering on events (See Figure 1) Since a RTD is defined for a finite time period, an important question that arises in defining the semantics is the manner in which an infinite computation satisfies a timing diagram Fisler [13] considers two kinds of semantics: in the invariant semantics, the timing diagram must be satisfied at every state of a computation, while in the basic iterative semantics, the diagram must be satisfied iteratively, at points satisfying a precondition of the diagram. Our semantics is a ....

....that this framework permits efficient model checking of timing specifications that are used in practice. Our review of industrial data books and discussions with engineers indicate that RTD s are sufficiently expressive for most industrial verification needs. With the exception of Fisler s work [13, 14], where the model checking algorithms have high complexity, other prior work considers timing diagram models that are at most as expressive as RTD s. The algorithm is linear in the structure size, polynomial in the number of diagram points and dependencies and in the unary size of the constants. ....

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K. Fisler. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Computer Science Department, Indiana University, August 1996.

....falling edge (falling edge triggered) In the SRTD in Figure 1, signals p and r are falling edge triggered while q is rising edge triggered. Timing diagrams may either be unambiguous, where the events are linearly ordered, or ambiguous, where the events are partially ordered with respect to time [11]. Synchronous timing diagrams are generally unambiguous but the don t care transitions do introduce some degree of ambiguity in SRTD s. 2.1 Syntax In most applications of timing diagrams, the waveform behavior specified by the diagram must hold of a system only after a certain precondition ....

K. Fisler. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Computer Science Department, Indiana University, August 1996.

....through diagrams, sketches and charts is so ubiquitous in human communication that it has long been desired to have automated reasoning systems taking visual representations as inputs. More generally, research effort has been devoted to developing logics for diagrammatic reasoning. For example, [Fisler, 1996] has developed a heterogeneous logic for hardware verification of design diagrams. A visual representation has also been used in the teaching of classical logic itself [Barwise Etchemendy, 1995] DARPA s High Performance Knowledge Bases (HPKB) program provided us with an excellent opportunity ....

Fisler, K. 1996, A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD Dissertation. Indiana University Department of Computer Science, August.

....accurate description of the timing diagram. This way, the user gets something in return for their effort. But we also log all their input attempts, thus creating a corpus of alternative ways of describing particular timing diagrams. An example of such a diagram is given in Figure 2 (adapted from Fisler 1996). The horizontal axis of the diagram indicates the passing of time (as measured by clock cycles) and the vertical axis indicates the transition of signals between the states of high and low. A signal is a timevarying value present at some point in the circuit. In Figure 2, the input signal sigi ....

Fisler, K. (1996) A Unified Approach to Hardware Verification through a Heterogeneous Logic of Design Diagrams. PhD thesis, Department of Computer Science, Indiana University.

....interval logic) which is a visual logic with formulae that resemble timing diagrams. A very important property of this logic (and the supporting tool set) is that it is a real time logic, which allows visual reasoning. Another extensively studied class of visual specifications is reported in [12]. One strong aspect in this work is the strive to make timing diagrams more expressive, for instance by allowing variables (with quantification) in timing annotations. This makes the formalism much more expressive (at the price of higher verification complexity when this feature is used) A third ....

K. Fisler. A Unified Approach to Hardware Verification Through a Heterogenous Logic of Design Diagrams. Dissertation, Indiana University, 1997.

....clocks for which containment by a regular language is decidable. 2 Timing Diagrams and Their Languages This work uses a formal logic of timing diagrams (called TDL) developed as part of our study of diagrammatic representations as formal specification languages for design and verification [5]. Starting from fairly common timing diagram notations, we define timing diagram semantics relative to formal languages. TDL is expressively incomparable to existing temporal logics such as LTL. In particular, LTL cannot express parametric timing constraints, while TDL cannot express properties ....

....because there is no way to stop the repeated searches at a particular point. TDL can not express G(p q) because it is not possible to make disjunctive statements within a TDL timing diagram. In separate work, we are investigating calculi over timing diagrams that would relax these restrictions [5]. Due to space constraints, only the invariant semantics is defined in the remainder of this section. The iterative semantics is defined formally in [5] Tuples hT; S; Xi capture a timing diagram, its set of assumed time points, and its fixedlevel constraints; the term timing diagram is ....

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Kathryn Fisler. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Indiana University, August 1996.

....temporal ordering on events; optional annotations on arrows specify discrete bounds on the time passing between the two events. Vertical parallel lines specify event synchronization. The annotation on the falling transition on b (an anchor) indicates that the transition happens at time t. Fisler [11] defines a formal syntax and semantics, as well as inference rules, for timing diagrams. or guarantee consistency after extensions. Others issues are architectural , such as how to integrate the code for existing subsystems. Architectural decisions greatly affect the maintainability and usability ....

.... the techniques described in this paper, we have built an extensible theorem prover called Ciderproof (see Figure 10) Ciderproof supports a logic of hardware design representations, including circuit diagrams, state machines, timing diagrams, linear temporal logic, and monadic second order logic [11]. Such logics, which support multiple syntactic representations (without embedding them in one another) are called heterogeneous [5] or multi language [15] They are ideal for problem domains, such as hardware design, in which people use multiple notations on individual problems. Since the ....

Fisler, K. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Indiana University, 1996.

....algorithmically against designs with infinite behaviors. This is significant because timing diagrams express different properties than the formalisms currently used in automated verification. A preliminary version of this result, covering only designs with finite behaviors, appeared previously [8, 10]; the extension to infinite behaviors is new. Our results also provide preliminary insight into the potential role of diagrammatic representations in algorithmic verification. Although human factors in design practice inspired our research into diagrammatic representations, we are interested in ....

....= k 4 Figure 5. A pseudo timing diagram, showing a language that well formed timing diagrams cannot express. Performing such reductions requires the ability to test containment between timing diagram languages. Timing diagrams without parametric timing constraints correspond to regular languages [10]; containment, and hence decomposition, is therefore decidable for such diagrams. Unfortunately, our current decision procedures are insufficient for addressing containment between arbitrary timing diagram languages, finite or infinite. Assume we want to test containment between the languages of ....

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Kathryn Fisler. A Unified Approach to Hardware Verification Through a Heterogeneous Logic of Design Diagrams. PhD thesis, Indiana University, 1996.

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Kathryn Fisler. 1996. A Unified Approach to Hardware Verification through a Heterogeneous Logic of Design Diagrams. Ph.D. thesis, Department of Computer Science, Indiana University.

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