Y.-A. Chen and R. E. Bryant. Verification of floating point adders. In CAV'98, volume 1427 of LNCS, 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... function and sticky bit computations is similar to [14] Russinoff does not cover denormals, exceptions, and round decomposition; however, he states that he handles denormals in unpublished work (private communication) There are other verification projects for floating point hardware, e.g. [1, 5, 16]. All these projects use less intuitive formalizations of IEEE rounding. They do not cover denormals and exceptions. 2 Factorings 2.1 Basic Definitions We abstract IEEE numbers as defined in the standard to factorings. A factoring is a triple (s, e, f) with sign bit s 1 , exponent e and ....

Y.-A. Chen and R. E. Bryant. Verification of floating point adders. In CAV'98, volume 1427 of LNCS, 1998.

....have no direct counterpart to the decomposition theorem and equivalence (cf. Sect. 2) They do not cover the actual implementation of operations or rounding. Aagaard and Seger combine BDD based methods and theorem proving techniques to verify a floating point multiplier [1] Chen and Bryant [4] use word level SMV to verify a floating point adder. Exceptions and denormals are not handled in both verification projects. Verkest et al. verify a binary non restoring integer division algorithm [28] Clarke et al. 7] and Ruess et al. 23] verify SRT division algorithms. Miner and Leathrum ....

Y.-A. Chen and R. E. Bryant. Verification of floating point adders. In CAV'98, volume 1427 of LNCS, 1998.

.... function and sticky bit computations is similar to [14] Russinoff does not cover denormals, exceptions, and round decomposition; however, he states that he handles denormals in unpublished work (private communication) There are other verification projects for floating point hardware, e.g. [1, 5, 16]. All these projects use less intuitive formalizations of IEEE rounding. They do not cover denormals and exceptions. 2 Factorings 2.1 Basic Definitions We abstract IEEE numbers as defined in the standard to factorings. A factoring is a triple (s; e; f) with sign bit s 2 f0; 1g, exponent e 2 Z, ....

Y.-A. Chen and R. E. Bryant. Verification of floating point adders. In CAV'98, volume 1427 of LNCS, 1998.

....This technique is improved in [9] by theorem proving methods to support an arbitrary register size and number of function units. There are many publications on the verification of (parts of) floating point units. Bryant and his group verified different function units using model checking [10 12]. Aagaard and Seger verified a multiplier using model checking combined with theorem proving [13] Claesen et.al. and O Leary et.al. have used theorem provers to verify supported by the DFG graduate program Effizienz und Komplexitat von Algorithmen und Rechenanlagen an SRT integer divider ....

Y.-A. Chen and R. E. Bryant. Verification of floating-point adders. Lecture Notes in Computer Science, 1427, 1998.

....is not active) For the close case, the result of mantissa subtraction requires a massive left shift (i.e. LZA is active) which makes the verification harder. Thus, the specifications of the close case must be divided further based on the number of bits to be left shifted. Readers can refer to [6] for the details of these specifications. 4.2 Specification Coverage Since the specifications of floating point adders are split into several hundred subspecifications, do these sub specifications cover the entire input space To answer this question, one might use a theorem prover to check the ....

CHEN, Y.-A., AND BRYANT, R. E. Verification of floating-point adders. Tech. Rep. CMUCS -98-121, School of Computer Science, Carnegie Mellon University, 1998.

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Y.-A. Chen and R. E. Bryant. Verification of floating point adders. In CAV'98, volume 1427 of LNCS, 1998.

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Y. Chen, and R. E. Bryant, "Verification of Floating-Point Adders", Computer Science Department, School of Computer Science, Carnegie Mellon University, 1998.

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