S. Keshav and R. Sharma, "Issues and Trends in Router Design," IEEE Communications Magazines, May 1998.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... T HE implementation of packet fair queuing (PFQ) schedulers, which aim at approximating the generalized processor sharing (GPS) policy [5] 8] is a central issue for providing multimedia services with various quality of service (QoS) requirements in ATM switches and next generation IP routers [1], 2] The objective is to design an efficient and scalable architecture that can support hundreds of thousands of sessions (virtual channels in ATM or flows in IP) in a cost effective manner. The GPS is an ideal weighted fair queuing service policy based on a fluid flow model. It can provide ....

S. Keshav and R. Sharma, "Issues and trends in router design," IEEE Commun. Mag., pp. 144--151, May 1998.

....put increasing demands on the routers and switches in the network for high bandwidth and low latency. In addition, as networks provide new services supporting multicast, voice, security, and bandwidth reservation, quality of service (QoS) is becoming a major issue in the design of routers [25] [18]. Fairness in resource allocation is very important to support the need for diverse applications. Fair queuing algorithms have been developed [8] 38] to schedule packets at an output link of a router. However, little research has been done to address QoS issues inside the router operation ....

S. Keshav and R. Sharma, "Issues and Trends in Router Design," IEEE Comm. Magazine, pp. 144-151, May 1998.

....process is a part of the real time and the non real time packet handling. Typically, the determination of the application set (Network Application Profile, NAP) would be done o# line whereas the determined NAP would be used in conjunction with the flow and packet classification systems [10], 7] 11] 12] 13] 14] in real time fashion. The first explicit information on the sending application in the Internet appear at the TCP UDP source and destination numbers. An IP application is, in this work, defined to be a group of packets originating from an identical source (TCP UDP) ....

S. Keshav and Rosen Sharma, "Issues and trends in router design," IEEE Communications Magazine, vol. 36, no. 5, pp. 144--151, May 1998.

....and f ixwest trace, respectively. The cisco trace is a 20 minute trace collected from a 100 BT cam pus network at Cisco Systems Inc. on March 4, 1997. The lbl trace is a 16 minute trace collected from a 100 BT at Lawrence Berkeley Laboratory (LBL) on July 14, 1997. The fixwest trace is a 20 minute trace collected from the FDDI Internet backbone at FIXWEST on Oct. 21, 1996. The utilizations at the time of data collections are 5.5 , 4.0 , and 27.3 , resp ectively. First, we need a flow cache entry timeout mechanism. We use a simple adaptive flow entry timeout algorithm as proposed ....

....from a 100 BT cam pus network at Cisco Systems Inc. on March 4, 1997. The lbl trace is a 16 minute trace collected from a 100 BT at Lawrence Berkeley Laboratory (LBL) on July 14, 1997. The fixwest trace is a 20 minute trace collected from the FDDI Internet backbone at FIXWEST on Oct. 21, 1996. The utilizations at the time of data collections are 5.5 , 4.0 , and 27.3 , resp ectively. First, we need a flow cache entry timeout mechanism. We use a simple adaptive flow entry timeout algorithm as proposed in [5] Namely, the timeout value Tn is periodically re assigned at time n ....

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S. Keshav and R. Sharma, "Issues and Trends in Router Design," IEEE Communications Magazine, May, 1998.

....of L bits sec is defined to be the product NL bits sec. Thus, high aggregate bandwidth switches can be designed in two ways: a small number of ports (small N ) connected to very high speed lines (large L) and a large number of ports (large N ) connected to slower lines (small L) As discussed in [10], the former type of switch typically resides in a core router , interconnecting a small number of enterprise networks via high speed lines. The latter type of switch resides in an edge router , which typically has a large number of ports running at relatively lower speeds. There are two main ....

Keshav S., Sharma R., "Issues and trends in router design", IEEE Communications Magazine, vol. 36, n. 5, May 1998, pp.144-151

....protocol number, source address, destination port and source port. Therefore, these protocols are even more time consuming. The number of memory accesses and the speed of the memory determine the speed of a route lookup algorithm. Various techniques have been proposed to improve route lookup time [Kesh98]. They can be broadly classified into: 4.1 Tree Based Algorithms Each node in the tree from root to leaf corresponds to an entry in the forwarding table and the longest prefix match is the longest path in the tree that matches the destination address of an incoming packet. In the worst case, it ....

....QOS mechanisms. Therefore, the traditional approach was that all the sophisticated techniques should be in the end systems and network should be kept as simple as possible. But recent research and advances in hardware capabilities have made it possible to make networks more intelligent. [Kesh98][Vijay98] 5.1 Components of Differentiated Services Following operations need to be performed at a high speed in the router to provide differentiated services: Packet classification, which can distinguish packets and group them according to different requirements. Buffer management, which ....

S. Keshav, R. Sharma, "Issues and Trends in Router Design, ", IEEE Communications Magazine, May 1998, pp.144-151, http://www.cs.cornell.edu/skeshav/papers/routertrends.pdf

....and unresolved issues in QoS routing. 2.0 Design of a QoS Router A router is a network device that transfers the data from the end host to a desired location in an optimal manner. It has essentially four components, namely input ports, output ports, switching fabric and a routing processor [20]. The switching fabric connects the input ports to the output ports. Input ports are the entry points for incoming packets while output ports are the exit points for the outgoing packets. The routing processor participates in the routing protocol and builds the forwarding table (also known as ....

S. Keshav, R. Sharma, "Issues and trends in router design", In IEEE Communications Magazine, May 1998, Vol. 36, No. 5, pp. 144-151.

....Among them, the longest prefix, which has the most specific routing information, is selected. Because this direct method is inefficient, many faster schemes have been suggested [1, 4, 5, 6, 11, 12, 13, 14] Most uses more memory to reduce the time. Routers can be classified into three categories [3]. Routers in access networks allow homes and small businesses to connect to an ISP(Internet Service Provider) Routers in enterprise network link computers within a campus or enterprise. Routers in the backbone link together ISPs and enterprise networks with long distance trunks. It is the ....

....2 describes previous works, and section 3 presents our proposed scheme. Section 4 discusses impact of routing instability to forwarding table update schemes. 2. Previous work The major performance bottleneck in backbone IP routers is the time taken to lookup a route in the forwarding table [3]. Because memory access is much slower than code execution, the lookup time depends primarily on the memory access time. In other words, the speed of a route lookup algorithm is determined by the number of memory accesses to find the matching route entry, and by the memory speed. By the memory ....

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S. Keshav and Rosen Sharma, "Issues and Trends in Router Design," IEEE Communications Magazine, May 1998.

....or more output links. The path and the service that packets receive in a network is determined by information stored in the packet headers, such as the source or destination addresses and the application port numbers. Figure 1 shows the basic architectural components of a conventional IP router [53]. Packets arrive at input links (input interfaces) and depart from output links (output interfaces) A routing protocol creates the routing table, which specifies the output interface(s) that a packet should be sent to. A packet switch, which can be a shared bus, a multi ported memory bank, or a ....

S. Keshav and R.Sharma, "Issues and Trends in Router Design," IEEE Communications Magazine, pp. 144--151, May 1998.

....IP QoS Model The main problem that makes IntServ infeasible was scalability. Maintaining thousands or millions of connections in an IntServ router is impractical. With the enormous number of sessions existing in the backbone, the amount of computation complexity involved overburdens the router [4]. Towards a solution, a new working group called DiffServ was formed to look into this issue. This group proposed a model that completely eliminated the storage of session states in the router[7] 8] The model is computationally inexpensive for a router even in the backbone. DiffServ implements ....

Rosen Sharma, S. Keshav "Issues and Trends in Router Design" IEEE Communications Magazine, pp. 144-151, May 1998

....meet the bandwidth demands both in the Internet backbone, and in enterprise backbones. The term for routers that employ Application Specific Integrated Circuits (ASICs) and can forward IP packets with the same throughput and deterministic behavior as an Ethernet or ATM switch, is Router Switch [19][21] Every Router Switch needs to incorporate the following functions: Packet Forwarding: Packet Forwarding is the process of looking at each incoming packet and deciding what output port it should go out on. This decision can be much more complex with questions about security, ....

S. Keshav, R. Sharma, "Issues and Trends in Router Design", in IEEE Communications Magazine , May 1998.

.... Flows would be removed from the list if no packet were received within a certain time out interval, as envisaged in the case of IP Switching [NLM96] This is certainly not an easy operation but one which does not seem to be outside the realms of possibility, given recent technological developments [KS98, KLS98]. To avoid the instability and inefficiency problems considered above, the admission control decision can be based simply on knowledge of the number of flows currently active on an outgoing link. This number could be deduced from the history of previous routing decisions and assumed flow ....

S. Keshav and R. Sharma. Issues and trends in router design, IEEE Commun. Mag., pp 144-151, May 1998.

....it is possible that new software technologies may decrease the performance of the router. Thus, it is not clear if these software technologies, while holding significant potential, will be practical, especially considering the current problems with maintaining port performance. Keshav and Sharma [1] note that the reduction of port cost is currently a tradeoff between application specific integrated circuits (ASICs) and general purpose processors. In this dichotomy, the only solution that provides reconfigurability is the use of a general purpose processor. Clearly, some other solution must ....

S. Keshav and R. Sharma, "Issues and Trends in Router Design," IEEE Communications Magazine, Vol.36, No.5, pp. 144-51, May 1998.

....(2) The new routers must support features like multicast, QoS, voice, security, etc. which increase the complexity of IP forwarding and therefore the time needed for each packet processing. Software processing at the routing processor is becoming the primary bottleneck in a router design[1, 2, 3]. To meet these requirements the new routers must become more complex and use more hardware resources and better algorithms. The designers must therefore be able to carefully examine their proposed solutions in terms of both performance and cost. Building the tools that enable an accurate ....

....at the network(router) processor due to software processing of the packets cannot accommodate the increased bandwidth. As a result, most high performance routers today employ advanced microprocessors and multiprocessors [8, 9] as the router architecture. However, the current simulation approaches[4, 5, 1], even with real traces, cannot evaluate the impact of architectural features, like instruction level parallelism(ILP) speculative execution, multiprocessing, and cache architectures on the performance of routers. Hence, we propose an execution driven simulation approach for the routers, where ....

S.Keshav and R.Sharma, "Issues and Trends in Router Design, " IEEE Communications Magazine, vol. 36, no. 5, pp. 144-151, May 1998.

....there has been a considerable amount of work showing that a form of input queueing (called virtual output queueing 1 (VOQ) can eliminate HOL blocking [2] 51] 66] A switch employing such a queueing discipline is known as a VOQ switch. VOQ switches, however, introduce another set of problems [33]. One of these problems is that VOQ switches require the use of a scheduler to configure the switch, deciding which input to connect to which output in each packet time. Because the scheduler determines exactly when each packet is transferred across the switch, the scheduler essentially determines ....

....need to maintain some queues at the outputs if they cannot immediately place all forwarded packets onto the outgoing links. More detail of queueing considerations is discussed in the following subsection. Because a packet switch implements the two tasks that a router also needs to perform [12][33][61] a router can take advantage of the high switching bandwidth already offered by a switch. Increasingly, high performance routers use a switch as a backplane to handle packet buffering and packet forwarding [2] 12] 53] 61] While packets arriving at a router may be of variable length, most ....

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Keshav, S.; Sharma, R.; "Issues and trends in router design," IEEE Communications magazine, May 1998, vol.36, no.5, pp. 144-151.

....router, IP networks, IP routers, parallel router, performance optimization, router architecture. I. INTRODUCTION T HE last three years have witnessed a rising interest in high performance routers as a very viable alternative to frame or cell forwarding switches in campus and backbone networks [1] [8] 1 Driven by the insatiable demand for bandwidth by customers and by the decreasing cost of technology, new generations of switched routers that support service differentiation over gigabit links have started to emerge [2] 4] 2 Also, recent innovations in fast route lookup through ....

....packetforwarding operations with the help of a master routing table maintained by the network processor. Among other things, the network processor is responsible for periodically updating the master routing table and for implementing a host of routing protocols (e.g. RIP, BGP, OSPF, IGMP, etc. [1]) The organization of a typical traditional router is shown in Fig. 1. It consists of a plurality of LC s, each supporting a number of link layer interfaces, such as Sonet OC 3, Sonet OC 12, Gigabit Ethernet, Fast Ethernet, etc. Each LC normally includes a simple satellite processor and a small ....

S. Keshav and R. Sharma, "Issues and trends in router design," IEEE Comm. Mag., pp. 144--151, May 1998.

....filters. The packet filters parse a portion of the packet header before forwarding decisions are made. The parsing is based on a set of rules defined by network management software or realtime reservation protocols and can be done using enhanced algorithms designed for fast packet classification [8, 17, 18, 19]. Flow classification is the equivalent of packet classification in another time scale: In packet classification we classify every packet whereas in flow classification we map the decision to some flow identifier (VC value, FlowId, etc. Inherently, the concept of flow classification comes from ....

S. Keshav and Rosen Sharma, "Issues and trends in router design," IEEE Communications Magazine, vol. 36, no. 5, pp. 144--151, May 1998.

....protocols. Choosing between ASICs and general purpose processors for an interface card is not straightforward. General purpose processors tend to be more expensive, but allow extensive port functionality. They are also available off the shelf, and their price performance ratio improves yearly [47]. ASICs are not only cheaper, but can also provide operations that are specific to routing, such as traversing a Patricia tree. Moreover, the lack of flexibility with ASICs can be overcome by implementing functionality in the route processor (e.g. ARP, fragmentation and reassembly, IP options, ....

....management) The router architecture should be optimized for those functions that must be performed in real time, on a packet by packet basis, for the majority of the packets. This creates an optimized routing solution that route packets at high speed at a reasonable cost. It has been observed in [47] that the cost of a router port depends on, 1) the amount and kind of memory it uses, 2) its processing power, and 3) the complexity of the protocol 42 used for communication between the port and the route processor. This means the design of a router involve trade offs between performance, ....

. S. Keshav and R. Sharma, "Issues and Trends in Router Design," IEEE Commun. Mag., May 1998, pp. 144 - 151.

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S. Keshav and R. Sharma, "Issues and Trends in Router Design," IEEE Communications Magazines, May 1998.

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S. Keshav and R. Sharma, "Issues and Trends in Router Design," IEEE Communications Magazine, vol. 36, no. 5, pp. 144--151, May 1998.

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S. Keshav and R. Sharma, "Issues and trends in router design," IEEE Commun. Mag., pp. 144--151, May 1998.

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S. Keshav and S. Rosen, "Issues and trends in router design," IEEE Communications Magazine, vol. 36, no. 5, pp. 144--151, May 1998.

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S. Keshav and R. Sharma, "Issues and trends in router design," IEEE Communications Magazine 36, pp. 144-- 151, May 1998.

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S. Keshav, R. Sharma, "Issues and Trends in Router Design", in IEEE Communications Magazine , May 1998.

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S. Keshav and R. Sharma, `Issues and Trends in Router Design', IEEE Communications Magazine, vol. 36 no. 5, pp. 144-151, May 1998.

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