F. Vahid, T. Le, and Y. Hsu, "Functional partitioning improvement over structure partitioning for packaging constraints and synthesis: Tool performance," ACM Trans. Design Automation Electronic Systems, vol. 3, no. 2, pp. 181-208, Apr. 1998.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....on a single device or because of I O pin limitations. Partitioning of a design can be done at various levels behavioral, register transfer level (RTL) or gate level. Behavioral partitioning is a presynthesis partitioning while RTL partitioning is done after high level synthesis. Various studies [1] show the superiority of behavioral over structural partitioning. A behavioral partitioner has no a priori knowledge about design parameters such as area and latency. The partitioner must be guided by a high level estimator that provides the required information. Efficient estimation techniques ....

F. Vahid. "Functional Partitioning improvements over Structural Partitioning for Packaging Constraints and Synthesis : Tool Performance". In ACM Transactions on Design Automation of Electronic Systems, volume 3, pages 181--208, April 1998.

....reducing power, functional partitioning also provides solutions to a variety of synthesis problems. These include I O satisfaction by reducing total I O by as much as 67 (which could impact physical design positively) reduced synthesis runtime by as much as 85 , and hardware software tradeoffs [9]. Furthermore, our technique does not require the modification of the synthesis tool. However, partitioning introduces extra power consumption for inter processor communication between the smaller parts. Thus, the problem that must be solved is one of partitioning such that the reduction in power ....

Frank Vahid, Thuy DmLe, and Yu-Chin Hus, "Functional Partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance," ACM Trans. Des. Autom. Electron. Syst. 3, 2, pp. 181-208, April 1998.

....packaging, physical design and debugging much easier, i.e. several smaller processes would be easier to work with than one large process. Recent experiments have verified this hypothesis. Synthesis runtime was reduced by 85 for numerous examples (reducing full day jobs into under an hour) [5]. The reductions occurred because synthesis uses non linear (e.g. quadratic) heuristics, so the sum of run times for synthesizing the parts is less than that for synthesizing the whole. Other experiments showed that power consumption was reduced by an average of about 50 [6] because each ....

....and reductions in total I O ranged from 27 to 67 , resulting in far fewer required parts to implement a system. Other advantages are also possible; for example, we have found performance improvements due to the smaller sub processors having shorter critical paths and hence faster clock periods [5]. Some have also observed that physical design problems, such as clock skew and the high cost of wires in deep submicron technologies, could be addressed using functional partitioning [7] The main drawback of functional partitioning is an increase (typically 20 in our examples) in gates because ....

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F. Vahid, T.D.M. Le, and Y.C. Hsu, "Functional partitioning improvements over structural partitioning for packaging constraints and synthesis-tool performance," ACM Transactions on Design Automation of Electronic Systems, vol. 3, no. 2, 1998.

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F. Vahid, T. Le, and Y. Hsu, "Functional partitioning improvement over structure partitioning for packaging constraints and synthesis: Tool performance," ACM Trans. Design Automation Electronic Systems, vol. 3, no. 2, pp. 181-208, Apr. 1998.

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