T. Shimizu, J. Korematu, et. al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," Proc. Int. Solid-State Circuits Conf., Feb. 1996, pp.216-217.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....4.2 Current Trends and Future Technology There are converging trends in the design of processors and memories that point to future existence of chips that include both processors and memory. Examples include Processors In Memory (PIM) Ko 94] Computational RAM [El et al. 92] IRAM [Pa 95, Sh et.al 96, Sa 96] Similar ideas were proposed as early as 1970 in [St 70] The driving argument for these approaches is the fact that the integration of CPU and memory on the same chip brings benefits of lower latency and higher bandwidth in accessing memory that outweigh possible reductions in the ....

....of the processor [Sa 96] Since memory access latency is becoming a limiting performance factor [Jo 95, Wi 95, WuMc 95] it is reasonable to expect that future generations of commercial chips will increasingly follow this trend. In fact, there are already some examples of such chips ( Sa 96, Sh et.al 96, AD 93] Two additional trends can be observed in the work mentioned in the last paragraph. One is the inclusion of hardware support for multiprocessor architectures in the integrated CPU memory chips [Sa 96] This means that they can be used as the basic blocks for building PAMs. The other is ....

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T. Shimizu, J. Korematu, et. al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," Proc. Int. Solid-State Circuits Conf., Feb. 1996, pp.216-217.

....As shown in Figure 1(a) the on chip memorypath consists of datapath, registers, SRAM cache, and DRAM main memory. High on chip memory bandwidth would be exploited between the cache and the main memory on cache replacement. Examples are Kyushu University s PPRAM R [5] Mitsubishi s M32R D[8], Sun s work [7] U. W. Madison s DataScalar[2] and so on. 2) DRM architecture (Figure 1(b) DRM (Datapath Register Main memory) borrows the concept from the vector architectures with vector registers such as Cray 1. As shown in Figure 1(b) the on chip memorypath consists of datapath, ....

Shimizu, T., et al. "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," Proceedings of the

....=2.0V 3 3 3 3 3 VCC =2.5V VCC =3.3V 2 2 2 2 2 Figure 4: Power Dissipation in the Output Pin multiprocessor board with wide bus between processor and main memory. The majority of the previous works are simple integration of MPU and DRAM based on MPU process or DRAM process [5]. However, the fabrication technology of MPU is different from that of DRAM as shown in Table 2. The target of MPU has been the performance, but, the target of DRAM has been density. Thus, the advances in design technology of MPU are mainly based on the multiple metal layer fabrication technology. ....

....and each block is corresponding to one image frame. From the analysis of DCT operation , the operations which are needed in the IRAM are summarized as below. Page 3 LOAD PE[0] 0] PE[7] 7] to R[0] R[63] 1 2 (R[0] SigmaR[7] to R[64] R[65] 1 2 (R[1] SigmaR[6] to R[66] R[67] 1 2 (R[2] SigmaR[5]) to R[68] R[69] 1 2 (R[3] SigmaR[4] to R[70] R[71] y 0 = P i=64;66;68;70 1 p 2 R[i] y 1 =c 1 R[65] c 3 R[67] c 5 R[69] c 7 R[71] y 2 =c 2 R[64] c 6 R[66] c 6 R[68] c 2 R[70] y 3 =c 3 R[65] c 7 R[67] c 1 R[69] c 5 R[71] y 4 =c 4 (R[64] R[66] R[68] R[70] y 5 =c 5 R[65] c 1 R[67] c 7 ....

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T. Shimizu and et al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," in ISSCC Digest of Technical Papers, pp. 216--217, Feb. 1996.

....disks has proven to be a challenge for disk manufacturers. Fortunately, there are products and research projects looking at integrating several components into a single chip processor, DRAM, and even networks thereby reducing some of these latencies and vastly increasing the bandwidth [77] [92]. One example project is Berkeley s IRAM, or intelligent RAM, project [77] Such integration reduces memory latency by factors of 5 to 10 and increases memory bandwidth by factors of 25 to 50 [77] This integration is also important to meet the power and size 143 restrictions of the disk ....

T. Shimizu, et al. "A multimedia 32 b RISC microprocessor with 16 Mb DRAM," ISSCC Digest of Technical Papers, pages 216-217, 448, Februrary 1996.

....technology can support the gigabit DRAMs, a single memory chip would cover the memory volume needed for the computer systems in the future. A number of studies (Aimoto et al. 1996; Elliott, Snelgrove, Stumm, 1992; Gokhale, Holmes, Iobst, 1995; Inoue, Nakamura, Kawai, 1995; Kogge, 1994; Shimizu et al. 1996; Yamashita et al. 1994) for the memory logic integration have utilized both high internal memory bandwidth and the available chip density. For computer graphics, a large amount of DRAMs and a small number of logic circuits are integrated into a 3 D DRAM chip (Inoue, Nakamura, Kawai, 1995) A ....

....integration have utilized both high internal memory bandwidth and the available chip density. For computer graphics, a large amount of DRAMs and a small number of logic circuits are integrated into a 3 D DRAM chip (Inoue, Nakamura, Kawai, 1995) A processor and memory integration onto a chip (Shimizu et al. 1996) and multiple instruction stream multiple data stream (MIMD) multiprocessors with their on chip local memories (Kogge, 1994) were proposed in order to overcome the low bandwidth to the local memory. Also, memory processor integrated arrays, such as computational RAM (C RAM) Elliott, Snelgrove, ....

Shimizu, T., et. al. (1996). A multimedia 32b RISC microprocessor with 16Mb DRAM, Dig. Tech. Papers, 1996 IEEE Int'l Solid--State Circuit Conf., pp. 216 -- 217.

....the current memory technology can support the gigabit DRAMs, a single memory chip would cover the memory volume needed for the computer systems in the future. A number of studies for the memory logic integration have utilized both high internal memory bandwidth and the available chip density [1, 2, 3, 4, 5, 6] In this paper an effective memory processor integrated architecture, called memory based processor array (MPA) for computer vision is proposed. It is an effective SIMD array which is based on the memory processor integration structure. Thus, it can be easily attached into any host system from ....

T. Shimizu, et. al, "A multimedia 32b RISC microprocessor with 16Mb DRAM," ISSCC96, pp. 216 217.

....completely. Instead, a timed cache line invalidation scheme is applied, marking as empty those lines that have not been accessed for more than the DRAM retention time. In a somewhat more aggressive design, Mitsubishi has integrated a RISC CPU with 2 MBytes of internal DRAM as the main memory[113]. An additional narrow interface to external memory is provided. However, such techniques fail to take advantage of the high bandwidth provided by the internal memory, leading to only modest performance benefits [14, 64] The IRAM project at Berkeley[105] is developing a high performance 11 ....

....macros described in [60] are based on the same DRAM core design, but come with 64 bit and 512 bit I O s, resulting in a large density difference, as summarized in Table 4.2. Lithography Technology Capacity Density Ref 1.00m 2 poly planar 1 Mb 13 (75.1) 110] 0. 45m Stack DRAM 16 Mb 169 (28.5) [113] 0.25m Stack eDRAM 64 Mb 264 (59.2) 124] Stack eDRAM 64 Mb 330 (47.3) 92] Stack eDRAM 16 Mb 697 (22.4) 3] 0.20m Trench eDRAM 16 Mb 745 (32.8) 60] Trench eDRAM 16 Mb 1,365 (17.9) 60] 0.18m Trench eDRAM 8 Mb 422 (71.4) 121] Stack eDRAM 32 Mb 1,406 (21.4) 145] 0.15m Trench eDRAM 16 Mb ....

[Article contains additional citation context not shown here]

T. Shimizu, J. Korematu, M. Satou, et al. "A multimedia 32b RISC microprocessor with 16Mb DRAM". In IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 8-10 February 1996. pp. 216--217.

....some form. The first DRAM based multiple node PIM chip was EXECUBE, fabricated in 1992 and supporting a 3D binary hypercube MIMD SIMD MPP on a single chip [Kogge94] Sunaga96] A more recent chip is the Mitsubishi M32 R D, where more than 2 MB of memory is tightly tied into the on chip CPU s cache [Shimizu96]. What stopped all these designs from becoming mainstream architectures is very simple memory density. Early PIM like devices used SRAM for memory, and even with relatively primitive MOS technology, it was quite easy to put more processing power on a single chip than the on chip data storage ....

Shimizu et al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," In International Solid State Circuit Conference, Feb. 1996, pp. 216-17.

....Processing RAM Chip with 256Mb DRAM and Quad Processors Kauzaki Murakami, Satoru Shirakawa, and, Hiroshi Miyajima Feb. 1997 PPRAM TR 13 Merged DRAM logic chips [1, 2] and architectures [3, 4, 5] are rapidly coming to our attention. Parallel Processing RAM (PPRAM) is an architectural framework for such merged memory logic ASSPs (Application Specific Standard Products) and integrates the following onto a single chip: 1) memory (a large amount of DRAM and or ....

Shimizu, T., et al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," ISSCC Digest of Tech. Papers, pp.216--217, Feb., 1996. PPRAM-TR-13 --- Kyushu University 3

..... Improve memory latency by factors of 5 to 10 and memory bandwidth by factors of 50 to 100, by redesigning the memory interface and exploiting the proximity of on chip memory [1] 2] Improve energy efficiency of memory by factors of 2 to 4, primarily by going off chip less frequently [3][4]; Reduce design effort tenfold by filling the die with replicated memory rather than with custom logic [5] Make the memory size and organization fit the intended workload; Reduce board area by factors of 4 or much greater by integrating many components on a single chip; and . Improve ....

Shimizu, T.; et al. "A multimedia 32 b RISC microprocessor with 16 Mb DRAM." ISSCC Digest of Technical Papers, San Francisco, CA, USA, 8-10 Feb. 1996 p. 216-17, 448.

....include a L2 cache that uses DRAM to increase size [Gia96] 2) Uniprocessors. This category combines a processor with on chip DRAM. This part might be attractive because of high performance, good power performance of the system, good cost performance of the system, or combinations of all three [Shi96] [Sau96] Benchmark perl li gcc hyfsys compress IRAM, 16:1 memory 1.0 1.7 1.8 2.3 1.7 IRAM, 32:1 memory 1.5 2.0 2.5 2.5 4.5 4. Related Work 18 3) Multiprocessors. This category includes chips intended exclusively to be used as a building block in a multiprocessor, IRAMs that include a MIMD ....

Shimizu, T.; Korematu, J.; Satou, M.; Kondo, H.; and others. "A multimedia 32 b RISC microprocessor with 16 Mb DRAM."Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 8-10 Feb. 1996 p. 216-17, 448.

....which notice merged DRAM logic LSI has been already proposed. Mitsubishi s M32R D integrates a 32b RISC processor, 2kB cache, 16Mb DRAM, and a memory controller. M32R D exploits high on chip memory bandwidth between processor and DRAM for improving the performance and reducing the power consumption[14]. UC Berkeley s Vector IRAM is an implementation of IRAM which means merged DRAM logic LSI. Vector IRAM includes sixteen 1,024 bit wide PPRAM TR 27 Kyushu University 7 SS SS SS SS S S S S SuperScalar Main Memory MPC Interconnet Network Main Memory Interconnet Network ....

Shimizu, T., et al. "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," 1996 ISSCC Digest of Technical Papers, pp.216--217, Feb. 1996.

....computations. 4.2 Trends and Future Technology There are converging trends in the design of processors and memories that point to future existence of chips that include both processors and memory. Examples include Processors In Memory (PIM) Ko 94] Computational RAM [El et al. 92] IRAM [Pa 95, Sh et.al 96, Sa 96] Similar ideas were proposed as early as 1970 in [St 70] The driving argument for these approaches is the fact that the integration of CPU and memory on the same chip brings benefits of lower latency and higher bandwidth in accessing memory that outweigh possible reductions in the ....

....of the processor [Sa 96] Since memory access latency is becoming a limiting performance factor [Jo 95, Wi 95, WuMc 95] it is reasonable to expect that future generations of commercial chips will increasingly follow this trend. In fact, there are already some examples of such chips [Sa 96, Sh et.al 96, AD 93] Two additional trends can be observed. One is the inclusion of hardware support for multiprocessor architectures in the integrated CPU memory chips [Sa 96] This means that these chips can be used as the basic blocks for building PAMs. The other is the inclusion of CPU cores on DRAM ....

[Article contains additional citation context not shown here]

T. Shimizu, J. Korematu, et. al., "A Multimedia 32b RISC Microprocessor with 16Mb DRAM," Proc. Int. Solid-State Circuits Conf., Feb. 1996, pp.216-217.

....set top boxes, multimedia processing systems, and much more. 2 1. M32R D Processor Features Mitsubishi Electric s M32R D is an industry first microprocessor with 2 MBytes of on chip DRAM (Hence the name eRAM Processor) with 4 KBytes of cache memory and a high performance on chip 128 bit bus [1]. eRAM processor bridges the processor memory performance gap via low latency and high bandwidth, and greatly improves the power performance and cost performance [4,5] M32R D has a small, powerful 32 bit RISC core with sixteen 32 bit general purpose registers and five stage instruction execute ....

T. Shimizu, J. Korematu, M. Satou, H. Kondo et. al, "A Multimedia 32 b RISC Microprocessor with 16 Mb DRAM", Digest of Technical Papers, 1996 IEEE International Solid-state Circuits Conference, San Francisco, CA, 8-10 Feb. 1996. pp 216-17, 448.

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T. Shimizu et al., "A Multimedia 32 b RISC Microprocessor with 16 Mb DRAM," Dig. Technical Papers, 1996 IEEE Int'l Solid-State Circuits Conf., IEEE, 1996 pp. 216-217, 448.

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