M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, and M. Yamashina. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In Symp. on VLSI Circuits Digest of Technical Papers, pages 55--56, June 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... capabilities of dynamically reconfigurable FPGAs such as [15] In order not to take too much time, presynthesized bit streams are generated at compile time and only these configuration streams are overwritten or simply swapped [4] at run time using techniques such as multi context FPGAs [8, 13]. The idea of reconfigurable hardware may, however, be spun further: In the software world, the first generations of microprocessors made use of the ingenious idea of selfreconfiguring program code stepwise in order to execute larger or more complex programs that would otherwise not fit into the ....

M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, and M. Yamashina. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In Symp. on VLSI Circuits Digest of Technical Papers, pages 55--56, June 1997.

....systems from academia that integrate DRAM and logic circuits have usually chosen the logic process path [13, 54, 115] probably because DRAM processes have not been widely available outside of the DRAM industry. On the other hand, industrial prototypes have often been based on DRAM processes [27, 61, 86]. Recently, embedded DRAM processes have appeared, in an effort to bridge the gap. These processes incorporate features of both logic and DRAM processes in order to achieve dense, high performance logic at the same time as dense DRAM. To date, there is no process that offers logic on par with a ....

....with very limited resources for inter page communication. Reconfigurable logic is not instrumental to the architecture and the Active Pages group is now turning its attention to integration of conventional processors into the memory[52, 94] Recently, NEC has designed an FPGA with integrated DRAM[86] in a very finegrain architecture. The highlight of this design appears to be the very fast reconfiguration, that is achieved by pitch matching the configuration memory of each logic block to the sense amplifiers of the neighboring memory bank. This makes it possible to achieve full ....

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M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, and M. Yamashina. "An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration". In IEEE Symposium on VLSI Circuits, Kyoto, Japan, 12-14 June 1997. pp. 55--56. 184

....such a design would require fully 50 of the available chip area for computational logic. All of the area figures in this paper assume a DRAM only process technology. Merged DRAM Logic (MDL) technologies would reduce our numbers by a factor of two if they become available in commodity memories [9]. Further study has shown that instruction level parallelism, not hardware specialization, is the key to our success with reconfigurable logic. Consequently, we have designed a simple No multiplexing 2 way multiplexing DRAM subarray processor VLIW 4 way multiplexing 8 way multiplexing ....

M. Motomura et al., "An embedded DRAM-FPGA chip with instantaneous logic reconfiguration," in 1997 Symposium on VLSI Circuits, 1997.

....into the device itself requires a larger amount of configuration memory in the device with respect to traditional approaches. For this reason, multi context FPGAs seem to answer better to these requirements, since they have been shown to be able to store a large amount of different contexts (see [12], for example, where a selfreconfiguring 256 context FPGA is presented) 3 Multicontext FPGAs As described in the Introduction, the time required to reconfigure a traditional FPGA is very high. To reduce the reconfiguration time, a device having more than one configuration context was proposed in ....

MOTOMURA, M., AIMOTO, Y., SHIBAYAMA, A., YABE, Y., AND YAMASHINA, M. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines (Napa, CA, Apr. 1998). Poster paper.

....3 Multicontext FPGAs As described in the Introduction, the time required to reconfigure a traditional FPGA is very high. To reduce the reconfiguration time, a device having more than one configuration context was proposed in [4] Several such multicontext FPGAs have been recently proposed [13][11][14] 8] 3] These devices have on chip RAM to store a number of configuration contexts, varying from 8 to 256. At any given time, one context governs the logic functionality and is referred to as the active context. Switching contexts takes 5 100 ns. This is several orders of magnitude faster ....

....of multicontext FPGAs: ffl The active context should be able to initiate a context switch no external intervention should be necessary. ffl The active context should be able to read and write the configuration memory corresponding to other contexts. The multicontext FPGAs described in [13][11][14] satisfy the above requirements and hence are capable of self reconfiguration 1 . 4 The KMP Algorithm for String Matching The String Matching problem consists of finding all occurrences of a pattern P , of length m, in a text T , of length n, m n, with P and T being strings over a finite ....

[Article contains additional citation context not shown here]

MOTOMURA, M., AIMOTO, Y., SHIBAYAMA, A., YABE, Y., AND YAMASHINA, M. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In 1997 Symposium on VLSI Circuits Digest of Technical Papers (June 1997), pp. 55--56.

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Masato Motomura et al. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In 1997 Symposium on VLSI Circuits, 1997.

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Masato Motomura et al. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In 1997 Symposium on VLSI Circuits, 1997.

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