A. DeHon. Multicontext fieldprogrammable gate arrays, 1997. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Adaptive Explicitly Parallel Instruction Computing - Talla (2000) (4 citations) (Correct)
....faster switching between CFU configurations, reducing idle time while the system waits for the CFU set to be altered. The idea of multiple configuration stores in FPGAs was first published in [133] DeHon later based his Dynamically Programmable Gate Array (DPGA) architecture around this idea [39, 159] and did a study of the benefits of multiple configuration stores in various applications [38] An earlier use of multiple configuration stores in a di#erent context was described by Snyder [34] In [163] the architecture of a time multiplexed FPGA is proposed. Eight configurations of the FPGA are ....
A. DeHon. Multicontext fieldprogrammable gate arrays, 1997.
String Matching on Multicontext FPGAs using.. - Sidhu, Mei, Prasanna (1999) (2 citations) (Correct)
....FPGAs As described in the Introduction, the time required to reconfigure a traditional FPGA is very high. To reduce the reconfiguration time, a device having more than one configuration context was proposed in [4] Several such multicontext FPGAs have been recently proposed [13] 11] 14] 8][3]. These devices have on chip RAM to store a number of configuration contexts, varying from 8 to 256. At any given time, one context governs the logic functionality and is referred to as the active context. Switching contexts takes 5 100 ns. This is several orders of magnitude faster than the time ....
....Match Counter Address Counter i Control logic char match state zero state final char match inc i next state inc state inc match Prefix function Figure 4: Datapath for Phase 2. state 2 state 1 state 0 zero state 3 state 4 state 5 state 5 state 0 state 1 inc state p[0] p[1] state 2 p[q] p[2] p[3] p[4] p[5] state 3 state 4 Figure 5: FSM template. The OR gate implements [1] 0. a state 0 state 1 inc state state 2 p[q] state 3 state 4 state 5 a b a b c Figure 6: Back edges built through OR gate insertion. Corresponds to FSM in Figure 3. the currently executing context cannot modify ....
DEHON, A. Multicontext Field-Programmable Gate Arrays. http://HTTP.CS.Berkeley.EDU/amd/- CS294S97/papers/dpga cs294.ps.
Adaptive Explicitly Parallel Instruction Computing - Surendranath Talla Of (2000) (4 citations) (Correct)
No context found.
A. DeHon. Multicontext fieldprogrammable gate arrays, 1997.
Scheduling on a Reconfigurable Processor with Virtual Pages - Caspi, Chu, Huang (Correct)
No context found.
Andr'e DeHon, "Multicontext fieldprogrammable gate arrays," draft, 1997. http://www.cs.berkeley.edu/~amd/CS294F98/ papers/dpgacs294.ps 10
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC